Hardware Task Scheduling for SOC Accelerator Latency Reduction
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Solution Overview
Problem
In intelligent driving systems, the increasing complexity of application programs requires high-efficiency and low-latency task scheduling, which is not effectively met by traditional CPU-based software scheduling methods, leading to high latency and frequent processor interruptions.
Innovation Solution
A SOC-based task scheduling method that uses hardware scheduling by implementing multiple task schedulers between the CPU and hardware accelerators, allowing direct scheduling of accelerators to execute tasks without CPU interruptions, thereby reducing latency to nanoseconds and improving system processing performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If CPU-based software scheduling is used, then system flexibility and programmability are maintained, but task scheduling latency is high and processing efficiency is low
Solution Approach 1:
The patent replaces the software-based scheduling mechanism with a hardware-based scheduling mechanism. Specifically, it introduces a task scheduler circuit and accelerator controller circuit that directly manage accelerator execution without requiring CPU software intervention. This substitution of software control with hardware control eliminates the time-consuming software execution path, thereby reducing task scheduling latency and improving scheduling efficiency.
Solution Approach 2:
The patent introduces an intermediary hardware component (the task scheduler circuit) that sits between the CPU and the accelerator. This intermediary receives task information from the CPU and directly controls accelerator execution, acting as a mediator that bypasses the need for continuous CPU software intervention. This intermediary structure enables faster task scheduling while maintaining system coordination.
2Productivity
If hardware scheduling is implemented, then task scheduling latency is reduced and efficiency is improved, but device complexity increases
Solution Approach 1:
The task scheduler circuit is designed to be multi-functional, handling both task allocation to accelerators and coordination with the CPU through a unified interface. The accelerator controller circuit also performs multiple functions including receiving task information, controlling accelerator execution, and managing data flow. This multi-functionality reduces the need for separate dedicated components, thereby limiting the increase in device complexity while achieving hardware-based scheduling.
Solution Approach 2:
The patent merges the task scheduling function and accelerator control function into an integrated hardware architecture. The task scheduler circuit and accelerator controller circuit work as a combined system, with the scheduler allocating tasks and the controller executing them, rather than using separate independent components. This merging approach reduces overall system complexity while still providing hardware-based scheduling benefits.
3Reliability
If CPU interrupts are used for task scheduling, then real-time task allocation is achieved, but processor performance is degraded due to frequent interruptions
Solution Approach 1:
The patent extracts the task scheduling function from the CPU by implementing a dedicated task scheduler circuit in hardware. This extraction removes the scheduling burden from the CPU, allowing the processor to focus on executing application tasks without being frequently interrupted by scheduling operations. The scheduler circuit independently handles task allocation, maintaining real-time scheduling capability while preserving CPU performance.
Solution Approach 2:
The hardware scheduling system is designed to be self-sufficient, with the task scheduler circuit autonomously allocating tasks to accelerators without requiring continuous CPU intervention. The accelerator controller circuit similarly operates independently to execute assigned tasks. This self-service capability enables real-time scheduling while freeing the CPU from frequent interrupt handling, thereby maintaining processor performance.
Data Source
AI summary
Disclosed are a SOC-based task scheduling method, a SOC, and an electronic device. The task scheduling method includes: determining a task set to be executed by the SOC and dependency relationships between respective tasks in the task set; determining, based on the task set and the dependency relationships, first scheduling information for a first task executable by a first accelerator in the SOC; transmitting, by a first task scheduler in the SOC, the first scheduling information to a second task scheduler, in the SOC, that is configured to schedule the first accelerator; and scheduling the first accelerator by the second task scheduler based on the first scheduling information, and executing the first task by the first accelerator.