Die-to-Die Bridge Circuit for High-Rate SoC-HBM Links
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Solution Overview
Problem
The integration of High Bandwidth Memory (HBM) with Systems on a Chip (SoC) is limited by spatial constraints, leading to restricted memory bandwidth and capacity, which hampers system performance in data-intensive applications, and requires rigid design modifications that restrict flexibility and adaptability.
Innovation Solution
Incorporating a bridge circuit with optimized interfaces between SoC and HBM, allowing for extended routing lengths and embedding digital logic within the bridge circuit to support high data rates, thereby breaking design constraints and enhancing bandwidth and flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If HBM is positioned adjacently to the SoC edge to ensure short electrical connections, then signal transmission quality is improved, but the periphery of the SoC becomes a restricting factor that limits the number of HBMs that can be integrated
Solution Approach 1:
An interposer is introduced as an intermediary component between the SoC and HBM stacks. The interposer provides a platform with multiple HBM stack locations that are not constrained by the SoC periphery, allowing multiple HBM stacks to be integrated while maintaining short electrical connections through the interposer's conductive pathways.
Solution Approach 2:
The system transitions from a 2D planar integration approach to a 3D stacked architecture. Multiple HBM stacks are vertically arranged on the interposer, utilizing the third dimension to increase memory capacity without expanding the horizontal footprint, thereby allowing more HBM integration while maintaining compact form factor.
2Quantity of substance
If the SoC size is expanded to accommodate more HBM, then memory capacity is improved, but manufacturing constraints are confronted and cost escalates
Solution Approach 1:
The memory system is segmented into separate HBM stacks that are independently manufactured and then integrated onto the interposer. This segmentation allows each HBM stack to be optimized and manufactured separately using standard processes, avoiding the need to manufacture a large monolithic SoC, thereby reducing manufacturing complexity and cost.
Solution Approach 2:
The interposer serves as a mediator that standardizes the interface between HBM stacks and the SoC. This standardization enables modular assembly where HBM stacks can be independently produced and then systematically integrated, simplifying the manufacturing process and reducing costs associated with custom large-scale SoC fabrication.
Data Source
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AI summary
The subject technology is directed to systems and methods for semiconductor devices with die-to-die interfaces. In an embodiment, the subject technology provides an apparatus that includes a first circuit (106, 206, 306) comprising a first interface (108, 308). The apparatus further includes a first memory device (118, 210, 318) coupled to the first circuit (106, 206, 306) through a second circuit (110, 208, 310). The second circuit (110, 208, 310) includes a second interface coupled to the first memory device (118, 210, 318) and a third interface (120, 320) coupled to the first circuit (106, 206, 306). The one or more interfaces of the apparatus are optimized to support a high data rate, breaking the design constraints between the circuit and the associated memory devices. There are other embodiments as well.