SoC Clock Selection With Hidden Crystal Backup for Glitch Handling

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Solution Overview

Problem

Existing clock generation systems in SoCs are vulnerable to tampering and safety failures, as they rely on external crystals that can be disrupted, leading to unauthorized access and safety issues.

Innovation Solution

A clock generation circuit within the SoC that dynamically selects between an external crystal and a hidden crystal, using glitch monitors to detect tampering or failures and switch to the hidden crystal as a backup, ensuring a secure and stable clock source.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If an external crystal is used for clock generation, then the clock source is easily accessible and can be tampered with, but the system becomes vulnerable to tampering attacks and safety failures

Engineering Contradiction:
ImproveAccessibility of clock sourceVSAvoidSecurity against tampering
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The clock source is segmented into two separate crystals: an external crystal for normal operation and a hidden crystal for security backup. This segmentation allows the system to maintain accessibility while protecting against tampering by isolating the secure backup clock source within the package substrate.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A clock selection circuit acts as an intermediary between the external and hidden crystals, dynamically selecting which clock source to use based on glitch detection. This intermediary mechanism enables seamless switching between clock sources without exposing the hidden crystal to external tampering while maintaining system operation.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If a hidden crystal is added as backup, then security and reliability are improved, but the device complexity increases

Engineering Contradiction:
ImproveBackup clock source availabilityVSAvoidNumber of clock sources and selection circuitry
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The hidden crystal and its associated glitch monitor are integrated within the package substrate alongside the SoC, merging multiple security functions into a single compact structure. This reduces the overall device complexity compared to having separate external components for each security function.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The system includes self-diagnostic capabilities through glitch monitor circuits that automatically detect tampering on both clock sources and trigger switching without external intervention. This self-service approach reduces the need for complex external control circuitry while maintaining high reliability.

Inventive Principle:
Principle #25Self-service

3Reliability

If dynamic clock source selection is implemented, then protection against tampering is achieved, but the circuit complexity increases

Engineering Contradiction:
ImproveTamper detection and switching capabilityVSAvoidClock selection and monitoring circuitry
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

Glitch monitor circuits provide continuous feedback on the integrity of both clock sources, enabling the clock selection circuit to dynamically adjust its output based on real-time security conditions. This feedback mechanism automates the security response without requiring complex external control logic.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The hidden crystal and its monitoring circuitry are pre-configured within the package substrate during manufacturing, with default switching logic already in place. This preliminary preparation eliminates the need for complex runtime configuration and reduces operational circuit complexity while maintaining security capabilities.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentEP4530792A1Clock generation with glitch detection and handling
Publication Date: 2025.04.02 NXP USA INC
  • EP4530792A1 patent drawingFigure 1
  • EP4530792A1 patent drawingFigure 2
  • EP4530792A1 patent drawingFigure 3

AI summary

In a system on a chip (SoC), clock selection circuitry provides a selected one of a first or second clock signal as an output clock based on at least one of a first flag and a second flag. This output clock is provided as a reference clock to one or more phase locked loops (PLLs) of the SoC. The SoC includes a first clock path which receives a first oscillating signal from a first clock source external to the SoC to generate the first clock signal, and a second clock path which receives a second oscillating signal from a second clock source external to the SoC to generate the second clock signal. A first glitch monitor asserts the first flag when a glitch is detected in the first oscillating signal, and a second glitch monitor configured asserts the second flag when a glitch is detected in the second oscillating signal.