Automated SOC Hierarchy Modification for Routing and Power Optimization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The complexity of System-on-Chip (SOC) designs, with large sizes exceeding 50 million gates, often leads to routing congestion and power distribution issues due to existing hierarchy structures, making manual restructuring of IP blocks error-prone and time-consuming, especially when integrating third-party IP blocks with unknown functionality.
Innovation Solution
A computerized method and system that automatically modifies the hierarchy structure of SOC designs by repositioning circuit elements and revising connectivity, allowing users to indicate movement, grouping, or ungrouping of IP blocks, while maintaining functional equivalence and optimizing power distribution and routing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If manual restructuring of IP blocks is performed to optimize routing and power distribution, then routing performance and power distribution are improved, but the process becomes error-prone and time-consuming
Solution Approach 1:
The system performs automatic hierarchy restructuring without manual intervention. The computer automatically analyzes the RTL netlist, identifies optimization opportunities, and repositions circuit elements based on power distribution and routing requirements, eliminating human error and significantly reducing restructuring time.
Solution Approach 2:
The patent replaces manual mechanical restructuring operations with automated computer-based analysis and modification. Instead of manually examining and repositioning each IP block, the system uses algorithms to automatically analyze the hierarchy and perform optimizations, transforming a labor-intensive process into an automated computational task.
2Device complexity
If hierarchy structure is modified to move circuit elements for better routing, then routing congestion is reduced, but connectivity between IP blocks must be carefully maintained
Solution Approach 1:
The system continuously monitors and analyzes connectivity relationships during the restructuring process. As circuit elements are repositioned, the computer automatically updates the netlist and verifies that all connections remain intact, providing real-time feedback to ensure connectivity is maintained while reducing routing congestion.
Solution Approach 2:
Before performing hierarchy modifications, the system analyzes the entire RTL netlist to identify all connectivity relationships. This preliminary analysis creates a complete map of connections that guides the restructuring process, ensuring that no connectivity is lost during element repositioning.
3Use of energy by moving object
If IP blocks are repositioned to optimize power distribution across voltage domains, then power efficiency is improved, but the hierarchy structure becomes more complex
Solution Approach 1:
The system applies different restructuring strategies to different parts of the hierarchy based on local requirements. IP blocks are repositioned within specific voltage domains to optimize power distribution, while maintaining appropriate hierarchy levels. This localized optimization improves power efficiency without unnecessarily complicating the overall hierarchy structure.
Data Source
AI summary
Systems and methods are disclosed for modifying the hierarchy of a System-on-Chip and other circuit designs to provide better routing and performance as well as more effective power distribution. A user specifies desired modifications to the design hierarchy and then the system automatically alters the hierarchy by performing group, ungroup, and move operations to efficiently and optimally implement the desired hierarchy modifications. Any modifications to port and signal names are automatically resolved by the system and the resultant RTL matches the function of the input RTL. The user then evaluates the revised hierarchy with regard to power distribution and routing congestion, and further hierarchy modifications are performed if necessary. A widget user interface facility is included to allow user-guided direction of hierarchy modifications in an iterative fashion.