SoC HiveSync Ready-Bit Synchronization for Multi-Processor Data Sharing

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Solution Overview

Problem

Existing system-on-chip (SoC) architectures face challenges in efficiently synchronizing data between heterogeneous processors due to reduced performance and power efficiency, particularly when data generated by one producer is consumed by multiple consumers, leading to restrictions on free connection and data sharing.

Innovation Solution

A system-on-chip (SoC) design incorporating a HiveSync monitor that manages buffer memory readiness using ready bits, allowing fine-grained synchronization of data units, enabling efficient data sharing and pipeline processing among multiple consumers without altering the internal structure of processors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If data sharing between heterogeneous processors is synchronized in buffer units, then data sharing is enabled, but performance and power efficiency are reduced

Engineering Contradiction:

Improvedata sharing capabilityVSAvoidprocessing performance

Core Design Contradiction:

Ease of operationVSProductivity

Solution Approach 1:

The patent segments the buffer memory into multiple fine-grained units, each with its own ready bit in the HiveSync monitor. This allows individual data units to be synchronized independently rather than synchronizing entire buffers, enabling parallel access and improving processing performance while maintaining data sharing capability.

Inventive Principle:

Principle #1Segmentation

2Ease of operation

If 1:1 connection in buffer is used for data sharing, then data sharing is simplified, but free connection between multiple producers and consumers is restricted

Engineering Contradiction:

Improvedata sharing simplicityVSAvoidconnection flexibility

Core Design Contradiction:

Ease of operationVSAdaptability or versatility

Solution Approach 1:

The HiveSync monitor with ready bits provides a universal synchronization mechanism that works for any combination of producers and consumers. Multiple producers and consumers can all access the same buffer units through the shared ready bit system, enabling flexible many-to-many connections without requiring dedicated 1:1 connection paths.

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Productivity

If fine-grained synchronization with ready bits is implemented, then processing efficiency is improved, but device complexity increases

Engineering Contradiction:

Improveprocessing efficiencyVSAvoidsynchronization mechanism complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent introduces the HiveSync monitor as an intermediary component between producers and consumers. This mediator manages the ready bits and coordinates access to buffer units, centralizing the synchronization logic in a dedicated structure rather than embedding complex synchronization mechanisms throughout the entire system, thereby improving efficiency while containing complexity growth.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS20250252039A1System-on-chip for synchronizing data between processors and memory sharing method thereof

Publication Date: 2025.08.07 SAMSUNG ELECTRONICS CO LTD

AI summary

Disclosed is a system-on-chip SoC, comprising, a host configured to generate job launching, a buffer memory, a producer configured to generate data in response to the job launching and store the generated data in the buffer memory, a consumer configured to read and process the data from the buffer memory in response to the job launching, and a HiveSync monitor configured to exchange at least one ready bit with the producer and the consumer indicating a readiness state of the data in the buffer memory, wherein the ready bit indicates the readiness state of the data divided into specific units.