SoC Interconnect Routing via Dynamic Access Port Assignment
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Solution Overview
Problem
In systems on a chip (SoC), the limited number of access ports compared to source devices leads to transaction routing congestion and inefficient memory usage, particularly when source devices have varying priorities.
Innovation Solution
A system on chip with an interconnect circuit and a control module that dynamically assigns access ports based on memory fill levels and source device priorities, using a hysteresis method to manage eligibility and prevent congestion, ensuring that transactions are routed efficiently by prioritizing source devices and optimizing memory usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the number of access ports is reduced to save resources, then device complexity and cost are reduced, but routing congestion and memory usage efficiency worsen
Solution Approach 1:
The patent implements dynamic access port assignment where the interconnect circuit continuously monitors memory fill levels and reallocates access ports based on current traffic conditions. This allows the system to adapt to varying transaction loads and source device priorities, preventing routing congestion even with fewer physical access ports
Solution Approach 2:
The system employs feedback mechanisms where the interconnect circuit receives status information about memory fill levels from access ports and uses this information to make intelligent routing decisions. This feedback loop enables the system to optimize memory usage and prevent congestion by redirecting transactions away from nearly full memories
2Productivity
If memory capacity of access ports is increased to reduce congestion, then routing efficiency improves, but device complexity and resource usage worsen
Solution Approach 1:
The interconnect circuit acts as an intermediary that coordinates between multiple source devices and access ports. It monitors memory fill levels and dynamically assigns access ports to source devices, effectively managing traffic flow without requiring each access port to have large memory capacity
Solution Approach 2:
The system maintains continuous monitoring of memory fill levels and continuous dynamic reassignment of access ports. This ongoing optimization ensures that memory resources are always utilized efficiently, preventing congestion without requiring excessive memory capacity at each access port
3Productivity
If priority-based routing is implemented for source devices, then transaction handling efficiency improves, but device complexity worsens
Solution Approach 1:
The system changes the parameter of access port assignment based on source device priority and memory fill level. The interconnect circuit uses these parameter changes to dynamically select which access port serves which source device, implementing priority-based routing through configurable assignment rules
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the risk of congestion and optimizes memory usage by dynamically managing access port assignments, ensuring that transactions are routed efficiently and prioritizing source devices based on their priority and memory availability.
Implementation Method 1
The control module is configured to receive the current fill signals from the memory of the access ports and select the access ports eligible to receive a transaction, depending on the current fill level of their associated memory
Data Source
AI summary
A system on chip includes an interconnect circuit including at least p input interfaces and at least k output interfaces, p source devices respectively coupled to the p input interfaces and k access ports respectively coupled to the k output interfaces and belonging to a target that includes one or more target devices. Each source device is configured to deliver transactions to the target via one of the access ports. An associated memory of each access port is configured to temporarily store the transactions received by the access port. The target is configured to deliver, for each access port, a fill signal representative of a current fill level of its associated memory. A control circuit is configured to receive the fill signals from the access ports and select the access ports eligible to receive a transaction depending on the current fill levels.