SoC Interconnect Traffic Dynamic Prioritization
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Solution Overview
Problem
In heterogeneous system-on-chip (SoC) environments, existing prioritization approaches struggle to dynamically manage quality of service (QoS) and power consumption across different types of processor cores, leading to inefficiencies in resource allocation and potential performance bottlenecks due to static prioritization methods.
Innovation Solution
The implementation of QoS control logic that dynamically adjusts priority levels for interconnect traffic based on inputs from both software and hardware, considering factors like transaction request priority, aging, system memory usage, and interconnect congestion, using a programmable algorithm to optimize resource allocation without interrupting the resource manager.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If static prioritization methods are used for interconnect traffic, then device complexity is reduced and ease of operation is improved, but quality of service and power consumption efficiency deteriorate
Solution Approach 1:
The patent implements dynamic prioritization where priority levels for interconnect traffic are adjusted in real-time based on system conditions. The QoS control logic continuously monitors factors such as transaction request priority, aging, system memory usage, and interconnect congestion, then dynamically modifies priority assignments without requiring complex reconfiguration of the entire system architecture.
Solution Approach 2:
The patent introduces a QoS control logic as an intermediary component that sits between the resource manager and the interconnect traffic. This mediator receives inputs from multiple sources (software and hardware), processes them through a programmable algorithm, and outputs adjusted priority levels, thereby isolating the complexity from both the resource manager and the traffic management mechanisms.
2Productivity
If dynamic prioritization based on multiple factors is implemented, then quality of service and resource allocation efficiency are improved, but device complexity and computational overhead increase
Solution Approach 1:
The QoS control logic is designed as a universal component that handles multiple functions: monitoring system memory usage, tracking interconnect congestion, evaluating transaction request priorities, and managing priority aging. By consolidating these diverse functions into a single multi-functional unit, the patent avoids the complexity of having separate mechanisms for each function while maintaining comprehensive control over resource allocation.
Solution Approach 2:
The patent employs a programmable algorithm that adjusts priority levels by changing parameters such as priority values, aging rates, and weighting factors for different input factors. This allows the system to adapt to varying conditions by modifying numerical parameters rather than restructuring the underlying logic, thereby improving resource allocation efficiency without proportionally increasing device complexity.
3Measurement precision
If continuous monitoring of system state is performed for dynamic prioritization, then prioritization accuracy and QoS are improved, but power consumption and processing overhead increase
Solution Approach 1:
The patent implements partial monitoring where the QoS control logic continuously monitors only the most critical factors (such as interconnect congestion and high-priority transaction requests) while periodically or event-driven monitoring of less critical factors (such as system memory usage). This selective monitoring approach maintains prioritization accuracy for time-sensitive operations while reducing overall power consumption and processing overhead compared to continuous full-state monitoring.
Data Source
AI summary
Embodiments of apparatuses and methods for dynamic prioritization of interconnect traffic in a system-on-chip are described. In an embodiment, an apparatus includes first circuitry to use a first weight value to weight operating system priority information to generate a first weighted priority value, second circuitry to use a second weight value to weight system-on-chip (SoC) hardware priority information to generate a second weighted priority value, third circuitry to sum the first weighted priority value and the second weighted priority value to generate a quality of service (QoS) value for an SoC interconnect transaction, and an arbiter to use the QoS value to prioritize the SoC interconnect transaction on an SoC interconnect.