SoC Interconnect Topology Synthesis via Window Segmentation
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Solution Overview
Problem
Designing a near-optimal interconnect network topology for complex System-on-Chip (SoC) with irregular floorplans and numerous IP blocks is challenging due to increased complexity and constraints on area, power, frequency performance, and bandwidth.
Innovation Solution
A method and system that synthesizes SoC interconnect network topology by representing it without a physical view, using multiple windows to simplify the design, and optimizing link routes by reordering elements and suggesting physical locations for links, while calculating metrics such as wire length and bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional approaches are used for SoC interconnect topology design, then the design process is simpler, but the topology quality (area, power, frequency performance, bandwidth) deteriorates for complex floorplans with many IP blocks
Solution Approach 1:
The patent divides the complex SoC floorplan into multiple smaller regions or clusters, each handled independently by the topology synthesis tool. This segmentation allows the tool to manage complexity by processing smaller subsets of IP blocks separately, then integrating the results into the complete interconnect topology.
Solution Approach 2:
The patent introduces an abstract topology representation layer that separates the logical interconnect design from the physical floorplan constraints. By working in this abstract dimension first, the tool can optimize topology metrics without being immediately constrained by physical layout, then map the solution back to the physical domain.
2Quantity of substance
If the number of IP blocks increases, then the functionality and performance of the SoC improve, but the difficulty of generating near-optimal interconnect topology increases
Solution Approach 1:
The patent segments the large set of IP blocks into smaller groups or clusters that can be processed independently. The topology synthesis tool applies optimization algorithms to each cluster separately, reducing the computational complexity from O(n) to O(n/k) where k is the number of segments, making it feasible to handle designs with many IP blocks.
Solution Approach 2:
The patent performs preliminary clustering and grouping of IP blocks based on their communication patterns and functional relationships before the main topology synthesis process. This preliminary organization reduces the search space for the optimization algorithms, making the subsequent topology generation more efficient and scalable to large numbers of IP blocks.
3Ease of manufacture
If detailed physical constraints are enforced during topology synthesis, then the implementation feasibility improves, but the optimization freedom and potential performance reduce
Solution Approach 1:
The patent introduces an intermediate abstract topology layer that decouples the optimization process from physical constraints. In this abstract dimension, the tool can explore a wider design space with greater flexibility. Once a near-optimal topology is found, it is then mapped to the physical domain where manufacturing constraints are applied, achieving a balance between optimization freedom and implementation feasibility.
Solution Approach 2:
The patent performs preliminary topology optimization in an abstract space with relaxed constraints, then applies physical manufacturing constraints as refinement criteria in a second pass. This two-stage approach allows the design to achieve near-optimal performance metrics first, then ensures manufacturability without sacrificing too much of the optimized performance.
Data Source
AI summary
A SoC interconnect network topology is represented. The corresponding SoC floorplan is divided into windows, which are contiguous and non-overlapping. Within each window a subnetwork of the SoC interconnect network topology is defined that includes links or communication paths between IP blocks in the window as well as links or communication paths that traverse the window. At the shared boundaries of the windows, ports are added and defined as virtual ports. The overall SoC topology can be optimized and synthesized by optimizing each window independently and then incrementally optimizing all links, from end-to-end, that traverse two or more windows. The SoC topology is edited, such as by adding switches, removing switches, and adding and removing switches on routes. An initial location of elements within the floorplan is automatically computed and recommended. Locations can also be edited. Statistical metrics are calculated, including wire length, switch area, SoC area, and maximum signal propagation rate. The SoC overall interconnect network topology is represented by the plurality of windows and the respective subnetworks of each widow. The windows are analyzed and combined and optimized to obtain an overall near-optimal SoC interconnect network topology.