SoC Interconnect Arbitration Using Virtual Channels and Flit Segmentation
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Solution Overview
Problem
The Advanced Microcontroller Bus Architecture (AMBA) standard for System on a Chip (SoC) arbitration is inefficient due to latency issues, as the bus interconnect is arbitrated on a transaction-by-transaction basis, leading to reduced efficiency and performance, as transactions cannot be interrupted and all non-winning transactions must wait until the current transaction is complete.
Innovation Solution
A method for arbitrating access to a shared interconnect on a clock cycle-by-clock cycle basis by using multiple virtual channels and dynamic priority schemes, allowing portions of transactions to be transmitted over these channels, thereby enabling interleaving and efficient resource allocation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If transaction-by-transaction arbitration is used, then simplicity of arbitration process is maintained, but latency increases and efficiency decreases
Solution Approach 1:
The patent segments transactions into flits (fixed-length data units) that can be independently arbitrated and transmitted. Instead of treating each complete transaction as a single unit, the transaction is divided into multiple flits that can be interleaved with flits from other transactions, allowing finer-grained arbitration and reducing latency while maintaining manageable complexity through systematic segmentation.
Solution Approach 2:
The patent introduces virtual channels as an additional dimension for transaction routing. Multiple virtual channels allow simultaneous transmission of different transaction flits across the same physical interconnect, effectively adding a temporal and logical dimension to the arbitration space. This enables parallel processing of transaction portions without increasing physical interconnect complexity.
2Reliability
If bus is controlled for entire transaction duration, then transaction integrity is ensured, but interconnect efficiency decreases
Solution Approach 1:
By segmenting transactions into flits, the patent allows the interconnect to release control of the bus after transmitting each flit, rather than holding it for the entire transaction duration. Each flit is independently arbitrated and transmitted, allowing other transactions to interleave their flits in between, thus improving interconnect efficiency while maintaining transaction integrity through proper flit sequencing and acknowledgment mechanisms.
Solution Approach 2:
The patent employs preliminary actions such as flit sequencing numbers, transaction identifiers, and acknowledgment protocols that are established before transaction completion. These preliminary structures enable the system to verify transaction integrity without requiring exclusive bus control for the entire duration, as each flit carries necessary metadata for validation and reassembly at the destination.
3Device complexity
If non-winning transactions wait for current transaction completion, then arbitration simplicity is maintained, but system throughput decreases
Solution Approach 1:
The patent segments transactions into flits that can be independently arbitrated. When one transaction wins arbitration, only its current flit is transmitted, while other transactions can simultaneously win arbitration for their respective flits in subsequent cycles. This eliminates the requirement for non-winning transactions to wait for complete transaction completion, thereby increasing system throughput while maintaining simple per-flit arbitration mechanisms.
Solution Approach 2:
The patent enables continuous useful action by allowing multiple transactions to progress simultaneously through flit-level arbitration. Instead of pausing non-winning transactions until current transactions complete, the system continuously arbitrates and transmits available flits from multiple transactions in parallel, maximizing interconnect utilization and system throughput without complicating the arbitration logic.
Data Source
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Figure 3A
AI summary
Arbitrating among portions of multiple transactions and transmitting a winning portion over one of a multiplicity of virtual channels associated with an interconnect on a clock cycle-by-clock cycle basis. By repeatedly performing the above each clock cycle, winning portions are interleaved and transmitted over the multiplicity of virtual channels over multiple clock cycles respectively.