SoC Interconnector Pipeline Arbitration Deadlock Prevention
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Solution Overview
Problem
System on chip (SoC) devices often experience deadlocks due to priority conflicts between requests from different master devices, leading to inefficient operation and potential system failure, as existing interconnector techniques struggle to effectively manage and prioritize transactions between master and slave devices.
Innovation Solution
The implementation of a system on chip with pointer update logic that processes requests from master devices sequentially in a pipeline manner, using a register slice unit and comparator to manage transaction IDs and directions, allowing for efficient arbitration and bypassing of conflicting requests, thereby preventing deadlocks and optimizing data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bus-based interconnector techniques are used to connect intellectual properties in a system on chip, then connection functionality is provided, but deadlock occurs due to priority conflicts between requests from different master devices
Solution Approach 1:
The patent applies preliminary action by pre-assigning priorities to different master devices before conflicts occur. The interconnector is configured with predetermined priority levels for each master device, allowing it to automatically resolve request conflicts without deadlock by always servicing higher-priority requests first, thus preventing the circular waiting condition that causes deadlock.
Solution Approach 2:
The interconnector serves as an intermediary between master devices and slave devices, managing request arbitration. It introduces a priority-based arbitration mechanism that mediates conflicts by selectively granting access to slave devices based on master device priorities, thereby preventing deadlock while maintaining system functionality.
2Productivity
If multiple outstanding address function is used to transfer multiple addresses simultaneously, then bandwidth utilization is improved, but request management complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the request management into separate priority levels and arbitration stages. Instead of managing all multiple outstanding addresses as a single complex queue, the interconnector segments request handling into priority-based lanes, where each priority level can independently manage its outstanding requests, simplifying overall control while maintaining high bandwidth utilization.
3Productivity
If data interleaving function is used to assign data from master IP to multiple slave intellectual properties, then bandwidth utilization is improved, but arbitration complexity increases
Solution Approach 1:
The patent applies preliminary action by pre-configuring priority relationships between master devices and slave devices before data interleaving operations begin. This allows the interconnector to automatically resolve arbitration decisions based on predetermined priorities, enabling efficient data distribution to multiple slaves without complex real-time arbitration logic.
Data Source
AI summary
A system on chip includes a plurality of master devices, a plurality of slave devices that supply data in response to requests of the plurality of master devices and pointer update logic configured to process the requests from the plurality of master devices sequentially in a pipeline manner.