SoC Interface Buffer for Clock Domain Crossing and Data Transfer
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In system-on-chip designs, conventional data transfer schemes and signal synchronization between functional blocks often do not coincide, necessitating an effective interface method for efficient data exchange.
Innovation Solution
An interface method involving circuit units that manage buffer allocation and resource values to transmit and receive payload data between functional blocks, allowing for data transmission and reception using IDs, QoS policies, and supporting different clock frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional data transfer schemes are used between functional blocks, then design simplicity is maintained, but data transfer efficiency and synchronization are degraded
Solution Approach 1:
The patent introduces a buffer as an intermediary component between functional blocks with different data transfer schemes. The buffer receives data from a first functional block using its native transfer scheme and outputs data to a second functional block using its required transfer scheme, thereby mediating the interface between incompatible blocks without requiring complex direct interfacing logic.
Solution Approach 2:
The patent extracts the data transfer scheme conversion function from the functional blocks themselves and places it in a dedicated buffer interface mechanism. This separation allows each functional block to operate with its own optimized transfer scheme while the buffer handles the conversion, reducing the complexity burden on individual blocks.
2Reliability
If buffer allocation is managed without resource value tracking, then allocation speed is fast, but data loss or overflow occurs
Solution Approach 1:
The patent implements a resource value tracking mechanism that provides feedback between the buffer manager and functional blocks. When a functional block requests data transfer, the buffer manager checks the current resource value (buffer availability) and either grants or denies the request based on this feedback, preventing overflow and ensuring data integrity while maintaining efficient allocation.
Solution Approach 2:
The patent performs preliminary resource value tracking and buffer availability checks before actual data transfer operations. By maintaining an up-to-date resource value that reflects current buffer status, the system can make immediate allocation decisions without requiring time-consuming runtime negotiations, thus ensuring reliability without significant time loss.
3Adaptability or versatility
If functional blocks operate at different clock frequencies, then system flexibility is improved, but synchronization difficulty increases
Solution Approach 1:
The patent uses the buffer as an intermediary that decouples the clock domains of different functional blocks. Data can be written to the buffer at the source block's clock frequency and read at the destination block's clock frequency, with the buffer handling the frequency translation and synchronization without requiring complex inter-block timing coordination.
4Reliability
If resource values are not tracked, then circuit simplicity is maintained, but buffer overflow or underflow occurs
Solution Approach 1:
The patent implements a self-service resource management mechanism where the buffer automatically tracks its own resource value (fill level) and uses this information to control data transfer operations. The buffer can autonomously determine when to accept new data, when to transfer data to destination blocks, and when to reject incoming data to prevent overflow, reducing the need for complex external control logic.
Data Source
AI summary
An interface method in a system-on-chip includes: a process of transmitting, by a first circuit unit, first payload data transferred from a first functional block and a first signal for requesting buffer allocation for storing the first payload data to a second circuit unit, and decreasing a resource value in which an initial value is set to correspond to the number of payload data which may be stored in a buffer provided in the second circuit unit by one; a process of storing, by the second circuit unit, the first payload data in the buffer according to the first signal; a process of withdrawing, by the second circuit unit, payload data selected among the payload data stored in the buffer, and transferring the payload data to a second functional block, and transmitting a second signal indicating that the buffer is empty to the first circuit unit; and a process of increasing, by the first circuit unit, the resource value by one.