SoC Interface Clock Gating for Low-Utilization Packet Paths
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Solution Overview
Problem
Conventional clock gating technologies in systems on chip (SoC) are inefficient as they supply clock signals to functional blocks not involved in information exchange, leading to increased power consumption due to complex signal paths and integration.
Innovation Solution
A system on chip with advanced clock gating cells and interface nodes that selectively gate clock signals based on control signals, ensuring clock signals are provided only to active nodes involved in packet transmission, using first and second clock control signals to manage clock signals for masters and slaves.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional clock gating technology gates clock signals in units of signal paths between masters, interconnects, and slaves, then the clock signal can be gated at the signal path level, but clock signals are still unnecessarily supplied to functional blocks not involved in information exchange, resulting in low efficiency and high power consumption
Solution Approach 1:
The patent segments the clock gating control into two independent dimensions: signal path level (via first clock control signal) and functional block level (via second clock control signal). This allows independent control of clock signals at different hierarchical levels, enabling precise gating that stops clock supply both to inactive signal paths and to functional blocks not involved in information exchange, thereby resolving the contradiction between energy efficiency and gating effectiveness
2Adaptability or versatility
If the number of functional blocks and signal paths increases to enhance system functionality, then the system on chip becomes more complex with more functions, but power consumption increases due to the increased number of signal paths and interconnects
Solution Approach 1:
The patent implements dynamic clock gating control where clock signals are selectively supplied based on real-time operational status. The first clock control signal dynamically gates clock signals at the signal path level based on information exchange activity, while the second clock control signal dynamically gates clock signals at the functional block level based on packet transmission completion. This dynamic control allows the system to maintain high functionality with multiple functional blocks and signal paths while reducing power consumption by suppressing clock signals only where and when they are not needed
Data Source
AI summary
A system on chip includes interface nodes and clock gating cells. A first interface node outputs first and second control signals having a first bit value based on a first packet, outputs the first packet based on a first clock signal, and outputs the first and second control signals having a second bit value based on first packet transmission. A second interface node outputs a third control signal in response to handshaking the first interface node, and receives the first packet from the first interface node based on a second clock signal. A first clock gating cell outputs the first clock signal based on an external clock signal and gates the first clock signal based on the first control signal. A second clock gating cell outputs the second clock signal based on the external clock signal and gates the second clock signal based on the second and third control signals.