SoC I/O Connectivity Verification with Low Power Constraints
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Solution Overview
Problem
Conventional formal verification techniques fail to accurately verify system on chip I/O connectivity due to the absence of low power design considerations, leading to erroneous results as they do not account for power on/off states in low power modes, which can cause undefined signals and invalid connectivity analysis.
Innovation Solution
A computer-implemented method and system that performs formal verification of system on chip I/O connectivity by generating combinational constraints based on low power design specifications, introducing isolation cells if necessary, and modifying the circuit to ensure valid connectivity under low power conditions, thereby considering power states of power domains during the verification process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional formal verification techniques are used to verify I/O connectivity, then the verification process is simple and fast, but the results are erroneous due to not considering low power design specifications
Solution Approach 1:
The patent applies preliminary action by generating combinational constraints from low power design specifications before performing formal verification. The system extracts power domain information and valid power state combinations in advance, then uses these constraints during verification to ensure accurate results while maintaining a systematic process
Solution Approach 2:
The patent uses an intermediary approach by introducing combinational constraints as a mediator between the low power design specifications and the formal verification process. These constraints act as a bridge that translates power domain requirements into verifiable conditions, enabling accurate connectivity verification without directly modifying the verification engine
2Reliability
If low power design specifications are integrated into formal verification, then verification accuracy is improved, but the verification process becomes more complex
Solution Approach 1:
The patent applies segmentation by dividing the verification process into distinct modules: one for extracting low power design specifications and generating combinational constraints, and another for performing formal verification using these constraints. This modular approach improves reliability by separating concerns while managing complexity through structured organization
Solution Approach 2:
The patent uses parameter changes by transforming low power design specifications into combinational constraints that parameterize the verification process. By converting power domain definitions and valid state combinations into constraint parameters, the system ensures reliable verification results while maintaining manageable complexity through parameterized processing
Data Source
AI summary
Formal verification of connectivity of a circuit, for example, a circuit representing a system on chip I/O ring is performed with low power considerations. The formal verification determines whether the connectivity of a circuit remains valid when low power design specification is introduced. The system receives assertions representing connectivity of the circuit. The system receives low power design specification for a circuit that describes power states of power domains of the circuit. The system generates combinational constraints representing valid power states of power domains of the circuit. The system performs formal verification based on the assertions representing the connectivity of the circuit and the combinational constraints representing the power states of power domains of the circuit. The result of the formal verification is used to determine whether the connectivity of the circuit is valid in view of the low power design specification.