SoC IO Pad Feedback Handshake for Reliable Wakeup Transitions
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Solution Overview
Problem
Conventional SoC integrated circuits experience wakeup failures due to improper latching of IO pad controls during standby mode entry, particularly when GPIOs are positioned far from the first input cell, leading to timing violations and inability to respond to wakeup signals.
Innovation Solution
Implement closed loop feedback with a latch acknowledge generation cell on the IORING side to ensure input buffer enable signals are latched before reset, using a special state machine on the SoC side to synchronize IO pad configurations with the core circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If IO pad controls are reset before latching during standby entry, then power saving is achieved, but wakeup failures occur due to improper latching state
Solution Approach 1:
The patent applies preliminary action by asserting the latch enable signal before resetting the IO pad controls during standby entry. This ensures that the IO pad controls are properly latched into their current state before the reset occurs, preventing wakeup failures while maintaining power savings. The sequence is: latch enable asserted → IO pad controls latched → reset applied → power reduced
Solution Approach 2:
The patent implements feedback through a handshake mechanism where the IORING side signals back to the SoC side when latching is complete. The latch acknowledge generation cell monitors the latching process and provides feedback signals (latch ack, latch ready) to the power control unit, ensuring that the reset and power reduction only occur after successful latching. This closed-loop feedback prevents timing violations and ensures reliable wakeup functionality
2Area of stationary object
If GPIOs are positioned far from the first input cell, then IORING size increases, but timing violations occur leading to wakeup failures
Solution Approach 1:
The patent uses feedback through the latch acknowledge generation cell that monitors latching completion and provides timing-synchronized signals back to the SoC side. This feedback mechanism ensures that regardless of GPIO distance from the first input cell, the latching and reset operations are properly synchronized, preventing timing violations even in large IORING configurations
Solution Approach 2:
The patent applies preliminary action by asserting the latch enable signal in advance before the reset signal reaches distant GPIOs. This preliminary latching action ensures that even GPIOs far from the first input cell have sufficient time to latch their states before reset, maintaining timing synchronization across large IORING areas
3Ease of operation
If asynchronous reset is applied before supply shutdown, then control logic is reset, but IO pad controls may be latched in incorrect states
Solution Approach 1:
The patent applies preliminary action by asserting the latch enable signal before applying the asynchronous reset. This ensures that IO pad controls are latched into their correct states before the reset occurs, preventing incorrect latching while still achieving control logic reset. The sequence maintains: latch enable first → IO pad controls latched → reset applied
4Loss of energy
If supply voltage is switched off immediately after reset, then power saving is maximized, but wakeup failures occur due to improper latching
Solution Approach 1:
The patent applies preliminary action by completing the latching sequence before switching off the supply voltage. The latch enable signal is asserted and maintained until latching is confirmed complete, ensuring IO pad controls are properly latched before power reduction. This prevents wakeup failures while achieving maximum power savings
Solution Approach 2:
The patent uses feedback through the latch acknowledge mechanism to determine when it is safe to switch off the supply voltage. The power control unit waits for latch acknowledge signals confirming successful latching before reducing power to the IORING, ensuring that wakeup functionality is preserved while maximizing power savings
Data Source
AI summary
System-on-Chip (SoC) integrated circuits, methods of operating such circuits, and methods and systems for avoiding wakeup failures relating to such circuits are disclosed herein. In one example embodiment, the present disclosure relates to a SoC integrated circuit that includes core circuitry including one or more control components, and peripheral input/output (IO) circuitry including an input circuit portion, a plurality of IO pads, and a feedback generation cell, which is configured to send at least one feedback signal to be received by the one or more control components in response to a first one of one or more intermediate signals sent by the input circuit portion. The one or more control components is/are configured to send, after the one or more control components have received the at least one feedback signal, one or more input buffer enable signals to be received by the IO pads to avoid a wakeup failure.