SoC IP Core Address Range Routing for Cache Efficiency
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Solution Overview
Problem
Conventional System on Chip (SoC) technologies experience low access hit rates and high power consumption due to the need for querying and matching all access commands in the system cache, leading to inefficient data retrieval from external memory.
Innovation Solution
The SoC incorporates an intellectual property core that obtains an address range configuration identifier for an access command, allowing the bus to route the command to either the system cache or external memory based on this identifier, thereby optimizing data processing and reducing unnecessary cache queries.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If querying and matching is performed in the system cache for all access commands, then the system cache can potentially return data directly, but the access hit rate is low and power consumption is high
Solution Approach 1:
The patent applies preliminary action by pre-configuring address range identifiers in the system cache that indicate which address ranges are suitable for caching. This allows the bus to make routing decisions based on pre-established criteria rather than requiring full cache querying for every access command, thereby reducing power consumption while maintaining high access hit rates for cacheable data ranges.
Solution Approach 2:
The patent changes the parameter of address identification by introducing address range configuration identifiers that classify different address ranges. This allows the system to differentiate between cacheable and non-cacheable address ranges, enabling selective routing that improves access hit rate for appropriate ranges while avoiding unnecessary cache operations for others, thus optimizing power consumption.
2Volume of moving object
If the system cache capacity is limited, then the cache can be implemented on-chip, but the access hit rate remains low due to insufficient cache capacity
Solution Approach 1:
The patent applies local quality by making different parts of the address space have different caching characteristics through address range configuration identifiers. This allows the system to optimize cache usage for specific address ranges that benefit from caching while avoiding waste on ranges that don't benefit, effectively increasing the usable cache capacity for relevant data and improving access hit rate within the limited on-chip cache volume.
3Use of energy by stationary object
If all access commands are routed through the system cache, then data can be returned from on-chip cache, but power consumption increases due to unnecessary cache operations
Solution Approach 1:
The patent applies segmentation by dividing the address space into different ranges with distinct caching characteristics using address range configuration identifiers. This segmentation allows the bus to route access commands directly to external memory for non-cacheable ranges while utilizing the cache for cacheable ranges, eliminating unnecessary cache operations and reducing power consumption without affecting data retrieval speed for either path.
Data Source
AI summary
A system on chip, an access command routing method, and a terminal are disclosed. The system on chip includes an IP core and a bus. The IP core is configured to: obtain, based on an access address corresponding to an access command, an address range configuration identifier corresponding to the access address; and transmit the access command and the address range configuration identifier to the bus, where the address range configuration identifier is used by the bus to route the access command. The bus is configured to route the access command to a system cache or an external memory based on the address range configuration identifier.