SOC LAN Ring Topology for Interconnecting Chips
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Solution Overview
Problem
Interconnecting distinct processing resources in data communication systems is complex, leading to increased costs, power consumption, and reduced performance due to the need for complex communication interfaces and data packetized protocols like Ethernet or SPI.
Innovation Solution
An interconnected processing system utilizing System On a Chip (SOC) integrated circuits with a media forming a SOC LAN ring and a routing address scheme that includes a source, destination, and LAN address, allowing for efficient data packet routing and rerouting across multiple SOC LAN rings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data packetized interfaces (Ethernet or SPI) are used to interconnect distinct processing resources, then communication between resources is achieved, but device complexity, cost, power consumption, and operation time increase
Solution Approach 1:
The patent divides the communication system into distinct SOC integrated circuits, each with its own processing resources and memory, interconnected via a simplified packetized interface. This segmentation allows each SOC to operate independently while maintaining simple communication protocols between them, reducing overall system complexity compared to using complex high-speed transaction interfaces.
Solution Approach 2:
The patent employs a universal packetized communication interface (Ethernet or SPI) that can interconnect multiple different processing resources across multiple SOC circuits. This universal interface replaces the need for specialized high-speed transaction interfaces, simplifying the communication layer while maintaining reliability across diverse processing resources.
2Reliability
If data packetized interfaces are used to interconnect distinct processing resources, then communication between resources is achieved, but cost and power consumption increase
Solution Approach 1:
By segmenting the system into multiple independent SOC circuits that communicate via packetized interfaces, the patent enables selective activation and efficient resource utilization. This reduces overall power consumption compared to maintaining always-on complex high-speed transaction interfaces, while preserving communication reliability.
3Reliability
If data packetized interfaces are used to interconnect distinct processing resources, then communication between resources is achieved, but operation speed decreases
Solution Approach 1:
The patent implements preliminary action by incorporating routing tables and address resolution mechanisms within each SOC circuit before communication occurs. This pre-computation of routing paths and address mapping enables faster packet forwarding and reduces communication latency, partially compensating for the inherent speed limitations of packetized interfaces compared to high-speed transaction interfaces.
Data Source
AI summary
A plurality of System On a Chip (SOC) integrated circuits, a media that intercouples the plurality of SOC integrated circuits to form at least one SOC LAN ring, and a routing address scheme. Each SOC integrated circuit includes at least one processor, a system bus, a memory controller, at least two Local Area Network (LAN) ports, and a receive channel selection block. The media intercouples the LAN ports of the plurality of SOC integrated circuits to form at least one SOC LAN ring. The routing address scheme serves in routing of data packets on the at least one SOC LAN ring. A routing address of the routing address scheme has a first portion that identifies a source SOC integrated circuit, a second portion that identifies a destination SOC integrated circuit, and a third portion that comprises a LAN address and data.