SoC Link Layer Protocol Virtual Channel Segmentation

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Solution Overview

Problem

Current network processors face challenges in maintaining coherent communications between multiple system-on-chips (SOCs), particularly in efficiently transmitting data messages across virtual channels and ensuring reliable data transfer with error handling and credit management.

Innovation Solution

The implementation of a data block transmission system across multiple SOCs, where data blocks are segmented and distributed across output ports, with credit counting and retry buffer mechanisms to ensure reliable transmission and error handling, utilizing a SCI protocol for coherent interconnect communications.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If data messages are transmitted across multiple virtual channels between SOCs, then data transfer capability is improved, but transmission reliability deteriorates due to increased complexity of coordinating multiple channels

Engineering Contradiction:
Improvedata transfer capabilityVSAvoidtransmission reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The data message is divided into multiple data blocks, each associated with a specific virtual channel. This segmentation allows independent transmission across multiple channels while maintaining reliability through per-block acknowledgment and retry mechanisms, resolving the contradiction between high-speed multi-channel transfer and transmission reliability.

Inventive Principle:
Principle #1Segmentation

2Speed

If data blocks are distributed across multiple output ports, then transmission speed is improved, but error handling complexity increases

Engineering Contradiction:
Improvetransmission speedVSAvoiderror handling complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The data stream is segmented into discrete data blocks that can be independently distributed across multiple output ports. Each block carries its own error correction information and acknowledgment mechanism, allowing parallel transmission at high speed while keeping error handling manageable through modular per-block error correction rather than system-wide complexity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system implements feedback mechanisms where receiving SOCs send acknowledgment signals back to transmitting SOCs for each data block. This feedback loop enables reliable error detection and correction without requiring complex centralized error handling, as each block is independently verified and retransmitted only if necessary.

Inventive Principle:
Principle #23Feedback

3Adaptability or versatility

If credit counting is implemented for each virtual channel, then data transfer control is improved, but system complexity increases

Engineering Contradiction:
Improvedata transfer controlVSAvoidsystem complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The credit counting mechanism is segmented and implemented independently for each virtual channel rather than as a monolithic system-wide controller. This allows flexible, adaptive control of data flow per channel based on buffer availability, improving data transfer control while limiting complexity to manageable per-channel implementations that can operate autonomously.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS9432288B2System on chip link layer protocol
Publication Date: 2016.08.30 MARVELL ASIA PTE LTD
  • US9432288B2 patent drawing
  • US9432288B2 patent drawing
  • US9432288B2 patent drawing

AI summary

A network processing system provides coherent communications between multiple system-on-chips (SOCs). Data messages between SOCs are assigned to virtual channels. An interconnect linking the SOCs divides the communications into discrete data blocks, each of which contains data segments from several virtual channels. The virtual channels can be implemented to control congestion and interference among classes of communications. During transmission, the interconnect distributes the data blocks across several physical ports linking the SOCs. As a result, communications between SOCs is optimized with minimal latency.