SoC Link Protection Circuitry for Secure Data Transmission
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Solution Overview
Problem
Conventional link protection methods for secure data transmission between a system on a chip (SoC) and devices via intermediate nodes require cryptographic hardware at each node, leading to increased latency, power consumption, and platform costs due to the need for encryption and decryption at each intermediate node.
Innovation Solution
Implementing end-to-end (E2E) link protection using cryptographic primitives like encryption and authentication with a shared key, where the SoC and devices handle encryption and decryption without relying on intermediate nodes, using link protection circuitry with encryption and decryption engines synchronized with counters to ensure data integrity and confidentiality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If cryptographic hardware is implemented at each intermediate node for link protection, then data security is improved, but latency increases due to encryption and decryption operations at each node
Solution Approach 1:
The patent extracts the cryptographic operations from intermediate nodes and concentrates them only at the source and destination devices. This removes the time-consuming encryption/decryption steps from the data path at intermediate nodes, thereby reducing latency while maintaining end-to-end security through authenticated encryption at the endpoints only.
Solution Approach 2:
The patent introduces authenticated encryption as a mediator that provides security without requiring intermediate cryptographic processing. By using encryption keys and authentication tags that travel with the data, the system achieves security protection through the data itself rather than through active cryptographic operations at each intermediate node.
2Reliability
If cryptographic hardware is implemented at each intermediate node for link protection, then data security is improved, but power consumption increases due to continuous encryption and decryption operations
Solution Approach 1:
The patent removes cryptographic processing requirements from intermediate nodes, extracting only the necessary security functions to the source and destination devices. This eliminates redundant power consumption at intermediate nodes while maintaining security through end-to-end authenticated encryption that requires minimal processing along the transmission path.
3Reliability
If cryptographic hardware is implemented at each intermediate node for link protection, then data security is improved, but platform costs increase due to additional hardware requirements
Solution Approach 1:
The patent extracts cryptographic hardware requirements from intermediate nodes and consolidates them only at source and destination devices. This significantly reduces platform costs by eliminating the need for cryptographic engines at intermediate nodes, while maintaining security through authenticated encryption implemented only at the endpoints where full cryptographic processing is necessary.
4Loss of time
If end-to-end link protection is implemented without intermediate cryptographic processing, then latency is reduced, but data security may be compromised without proper authentication mechanisms
Solution Approach 1:
The patent performs authentication preparation in advance by generating authentication tags along with the encrypted data at the source device. This preliminary action ensures that security verification can occur efficiently at the destination without adding latency, as the authentication mechanisms are already in place before transmission begins.
Solution Approach 2:
The patent uses authenticated encryption as a mediator that combines confidentiality and integrity protection in a single cryptographic operation. This approach maintains data security by ensuring both encryption and authentication without requiring separate processing steps, thereby achieving security without compromising the low-latency performance of end-to-end protection.
Data Source
Figure 1A
Figure 1B
Figure 1C~1D
AI summary
A system on a chip (SoC) includes memory, a processor coupled to the memory, and link protection circuitry coupled to the memory and the processor. The link protection circuitry includes an SoC encryption engine to receive first data from the memory and a first key, generate, by an SoC encryption counter of the SoC encryption engine, an SoC encryption counter value, encrypt the first data using the SoC encryption counter value and the first key to generate first encrypted data, and cause the first encrypted data to be transmitted to a device including a device decryption counter synchronized with the SoC encryption counter.