SoC Low Power Controller Hardware Event Analysis
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Solution Overview
Problem
Existing system on chip (SoC) technologies require software intervention to manage power, leading to increased load and time consumption, especially for short-duration tasks in mobile devices, which affects battery life due to inefficient power and frequency control.
Innovation Solution
A low power controller is introduced to automatically set power and operation frequency for predictable tasks, allowing the SoC to wake up and complete necessary operations without software intervention, using a parameter storage unit to analyze events and determine minimum voltage, frequency, and power gating settings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If software intervention (OS, power management program) is used to manage power and frequency, then power management flexibility and adaptability are improved, but power consumption increases and response time increases
Solution Approach 1:
The system uses hardware-based event analyzers and power management circuits that automatically detect events and control power/frequency without software intervention. The hardware self-manages power states by analyzing events and adjusting voltage/frequency accordingly, eliminating the need for OS-level power management software.
Solution Approach 2:
The patent replaces software-based power management (mechanical/system-level control) with hardware-based event analysis and control circuits. The hardware event analyzer and power management circuit directly control power and frequency based on detected events, substituting the software intervention layer with dedicated hardware logic.
2Adaptability or versatility
If software intervention is used to determine power and frequency settings, then adaptability to different tasks is improved, but response time increases due to software processing delays
Solution Approach 1:
The patent replaces software-based power management (mechanical/system-level control) with hardware-based event analysis and control circuits. The hardware event analyzer and power management circuit directly control power and frequency based on detected events, substituting the software intervention layer with dedicated hardware logic.
Solution Approach 2:
The system pre-configures power management parameters and event analysis rules in hardware before runtime. When events occur, the hardware event analyzer immediately matches them against pre-configured patterns and triggers appropriate power/frequency settings without requiring software interpretation or decision-making delays.
3Use of energy by moving object
If hardware-based automatic power control is implemented, then power consumption is reduced and response time is improved, but device complexity increases
Solution Approach 1:
The system divides power management into separate functional modules: event detection units for different event types (sensor, communication, user input), event analyzers for pattern recognition, and power management circuits for voltage/frequency control. This segmentation allows each module to be optimized independently and simplifies the overall control logic.
Solution Approach 2:
The hardware event analyzer and power management circuit are designed to handle multiple types of events (sensor events, communication events, user input events) and control multiple parameters (voltage, frequency, power gating) through a unified architecture, reducing the need for separate dedicated circuits for each function.
Data Source
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AI summary
A system on chip includes an event manager configured to receive an event from an external source, an event analyzer configured to analyze the event received by the event manager to determine a voltage, a frequency, and power gating corresponding to the analyzed event, a power manager configured to set power on or off and to set a voltage, a clock manager configured to set a clock frequency, a power gating (PG) manager configured to set power gating, a main controller configured to include at least one modules and a central processing unit (CPU), and a wakeup controller configured to control the power manager, the clock manager, and the PG manager, to transmit power having a starting voltage and a clock signal having a starting clock frequency, and to transmit a power gating signal to apply power only to one of the at least one modules operating so as to start the main controller.