SoC Low-Power Fabric Routing for Memory Debug Communication

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Solution Overview

Problem

Current graphics processors face challenges in debugging memory subsystem failures during low power states due to data transfer waking up low power state components, which alters system behavior and hinders proper debugging.

Innovation Solution

A system-on-a-chip (SoC) architecture with a low power state agent and memory bridge fabric agent enables communication during low power states, allowing data transfer without waking up components, using an alternate low power state fabric path.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If data transfer is performed through low power state components, then communication functionality is maintained, but the low power state components wake up and system behavior changes

Engineering Contradiction:

Improvedebugging accuracyVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by stationary object

Solution Approach 1:

A debug interface is introduced as an intermediary component that allows debugging operations to bypass low power state components. The debug interface receives debug requests from external debuggers and forwards them to memory subsystems without requiring the low power state components to wake up, thus maintaining system behavior while enabling debugging.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The system is segmented into normal operational paths and debug operational paths. The debug path is separated from the normal data transfer path, allowing debugging operations to be performed through dedicated debug interfaces that do not trigger wake-up events in low power state components.

Inventive Principle:

Principle #1Segmentation

2Use of energy by stationary object

If components are put into low power state to save energy, then power consumption is reduced, but data transfer capability is lost

Engineering Contradiction:

Improvepower consumptionVSAvoiddata transfer capability

Core Design Contradiction:

Use of energy by stationary objectVSEase of operation

Solution Approach 1:

The debug interface acts as a mediator that enables data transfer capability for debugging purposes without requiring the low power state components to become active. It provides a separate communication channel that works around the power state restrictions.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The system dynamically switches between normal operational mode and debug operational mode. During debug mode, the debug interface is activated to provide data transfer capability while keeping the main components in low power state. This dynamic adaptation allows the system to maintain different capabilities based on operational context.

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS20260037456A1System-on-a-chip (SOC) architecture for low power state communication

Publication Date: 2026.02.05 INTEL CORP

AI summary

An apparatus to facilitate a system-on-a-chip (SoC) architecture for low power state communication is disclosed. The apparatus includes a low power state fabric to provide a low power state path that avoids compute processing resources of the apparatus, and a low power state agent circuitry communicably coupled to the low power state fabric to update, in response to initiation of a low power state in the apparatus, a configuration of routers of the low power state fabric to utilize the low power state path provided by the low power state fabric, and to route memory transactions to the low power state path while the apparatus is in the low power state.