SoC System Time Clock Synchronization Without Gray-Code Conversion
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Solution Overview
Problem
Existing system time clock synchronization methods for System-on-a-Chip (SOC) require conversion of binary code to Gray code and back, leading to processing overhead and inefficiency due to the need for additional logic to encode and decode, especially in long wires.
Innovation Solution
The method employs LSB sampling to distribute system timer counts directly in binary format without conversion to Gray code, using a system timer clock slower than internal processor clocks, and triggers sampling based on the least significant bit change, allowing synchronization across processors with reduced processing overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If binary code is converted to Gray code and back for system time clock synchronization, then synchronization reliability is improved, but processing overhead and device complexity increase due to additional encoding and decoding logic
Solution Approach 1:
The patent extracts only the least significant bit (LSB) of the system time clock signal for distribution to processing elements, eliminating the need for complete binary-to-Gray code conversion. This selective extraction maintains synchronization reliability while removing complex encoding/decoding logic from the system.
Solution Approach 2:
Instead of converting the entire binary code to Gray code and back as traditionally done, the patent inverts the approach by directly sampling and distributing only the LSB in its native binary form. This reversal eliminates the conversion overhead while preserving the essential synchronization information.
2Reliability
If binary code is converted to Gray code and back for system time clock synchronization, then synchronization reliability is improved, but processing time and productivity decrease due to additional conversion steps
Solution Approach 1:
The patent extracts only the least significant bit (LSB) of the system time clock signal for distribution to processing elements, eliminating the need for complete binary-to-Gray code conversion. This selective extraction maintains synchronization reliability while removing complex encoding/decoding logic from the system.
Solution Approach 2:
The patent skips the traditional binary-to-Gray code conversion steps entirely by directly sampling and distributing the LSB. This rushing through of the essential synchronization information without unnecessary conversion steps significantly reduces processing time and increases throughput.
3Speed
If a faster system timer clock is used to synchronize processors, then synchronization speed is improved, but timing conflicts and metastability increase when processors have varying clock frequencies
Solution Approach 1:
Instead of using a fast system timer clock that risks timing conflicts with faster processor clocks, the patent inverts the approach by using a slower system timer clock. This ensures the system timer clock remains the master clock that all processors can reliably sample without timing conflicts or metastability issues.
Solution Approach 2:
The patent introduces the LSB sampling mechanism as an intermediary between the system timer clock and processor clocks. By sampling only the LSB and using it as a trigger signal, the system mediates the frequency difference between the slower system timer clock and faster processor clocks, ensuring reliable synchronization without direct timing conflicts.
Data Source
AI summary
Techniques for managing a system time clock within a processor are disclosed. A system-on-a-chip (SOC) is accessed. The SOC includes a system timer and one or more compute clusters. Each compute cluster includes one or more processors. Each processor includes an internal processor clock. The system timer generates a timer count based on a system timer clock. The timer clock is slower than every processor clock. The system timer count is sent to each compute cluster. The timer count is distributed by clusters to processors. Sampling logic is triggered within a first processor, based on a system timer count least significant bit (LSB) state change. Sampling logic within each processor samples the system timer count. The sampling occurs after a minimum of two cycles of each processor clock, following the triggering. The sampling obtains a current value of the system timer count.