SoC Mailbox in TCM for CPU Communication Latency
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Solution Overview
Problem
In conventional SoCs with multiple CPUs, frequent communication between CPUs leads to inefficiency due to longer signal delays caused by interface conversion through advanced high-performance buses (AHB) bridges.
Innovation Solution
Designing a mailbox within the level one memory system, allowing CPUs to directly access and read commands without going through the level two memory interface, thereby reducing the need for protocol conversion and address mapping, and simplifying the AXI interconnect by removing intermediate interfaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If the mailbox is accessed through the AHB bridge with interface conversion, then the CPU can communicate with peripheral memory/register, but the signal delay increases and communication efficiency decreases
Solution Approach 1:
The mailbox is extracted from the general memory system and placed in the TCM, allowing it to be accessed directly by the CPU core circuit without going through the AHB bridge and level two memory interface. This extraction eliminates the interface conversion step and reduces signal delay for mailbox access specifically.
Solution Approach 2:
The TCM is designed with special local quality characteristics - it is directly coupled to the level one memory interface and can be accessed with lower latency than general memory. By placing the mailbox in the TCM, we give it local quality that enables faster access compared to the general memory system.
2Productivity
If the mailbox is placed in the level two memory system, then the memory structure is simplified, but the communication frequency between CPUs is limited due to interface conversion requirements
Solution Approach 1:
The memory system is segmented into different levels with different purposes. The TCM is segmented as a special memory region directly accessible from the core circuit, while other memory remains in the level two system. This segmentation allows the mailbox to have fast access path without requiring complete restructuring of the entire memory system.
3Adaptability or versatility
If interface conversion through AHB bridge is used, then compatibility with standard memory interfaces is maintained, but the AXI interconnect complexity increases and performance decreases
Solution Approach 1:
The TCM acts as an intermediary structure between the AXI interconnect and the mailbox. Instead of requiring direct interface conversion through the AHB bridge, the TCM provides a intermediate access path that the CPU core circuit can use to communicate with the mailbox efficiently, reducing the complexity of the AXI interconnect.
Data Source
AI summary
The present invention provides a SoC including a first CPU, a first tightly-coupled memory, a second CPU and a second tightly-coupled memory is disclosed. The first CPU includes a first core circuit, a first level one memory interface and a first level two memory interface. The first tightly-coupled memory is directly coupled to the first level one memory interface, and the first tightly-coupled memory includes a first mailbox. The second CPU includes a second core circuit, a second level one memory interface and a second level two memory interface. The second tightly-coupled memory is directly coupled to the second level one memory interface, and the second tightly-coupled memory includes a second mailbox. When the first CPU sends a command to the second mailbox within the second tightly-coupled memory, the second core circuit directly reads the command from the second mailbox, without going through the second level two memory interface.