SoC Manager Architecture-Specific Debugging Bus
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Solution Overview
Problem
System-on-chip (SoC) processors with different architectures face challenges in identifying and extracting debugging information during deadlock states, as existing methods are inefficient and often require rebooting all components, making it difficult to determine the cause of the deadlock.
Innovation Solution
The SoC includes a plurality of processors with different architectures, an SoC manager that generates and transmits architecture-specific information extraction commands through a separate bus, and a debugging master that extracts and stores debugging information before rebooting, allowing for efficient identification of deadlock causes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a single unified debugging method is used for all processors, then the debugging process is simple, but it cannot effectively extract debugging information from processors with different architectures
Solution Approach 1:
The patent applies local quality by generating different information extraction commands tailored to each processor's specific architecture. The debugging master identifies the architecture type of each processor and selects or generates appropriate commands for that specific architecture, rather than using a single universal command set. This allows effective debugging information extraction from heterogeneous processors while managing complexity through targeted command generation.
2Loss of information
If debugging information is extracted after rebooting all processors, then the system is simplified, but debugging information is lost and deadlock causes cannot be identified
Solution Approach 1:
The patent implements preliminary action by extracting debugging information from processors before they are rebooted. When a deadlock is detected, the debugging master immediately generates and sends information extraction commands to the affected processors to capture their state data before the reset occurs. This preliminary data collection preserves crucial debugging information that would otherwise be lost, enabling efficient deadlock analysis without requiring multiple reboot cycles.
3Reliability
If a separate debugging bus is used for each processor, then debugging information extraction is reliable, but the system complexity and resource usage increase
Solution Approach 1:
The patent applies universality by using a single shared debugging bus that serves all processors in the system. The debugging master communicates with multiple processors of different architectures through this common bus, selecting and generating appropriate commands based on each processor's architecture type. This approach maintains reliable debugging information extraction while avoiding the complexity of multiple dedicated buses, as the same physical bus infrastructure supports all debugging operations across heterogeneous processors.
Data Source
AI summary
A system-on-chip (SoC) includes: a plurality of processors configured to store respective debugging information in response to respective information extraction commands received in a deadlock state, the plurality of processors having different architectures; a system bus connected to the plurality of processors; and an SoC manager configured to generate the respective information extraction commands differently according to an architecture of each of the plurality of processors in response to detecting occurrence of the deadlock state, and transmit the respective information extraction commands to the plurality of processors through a bus separate from the system bus.