SoC Master Device Access Resilience via Clock and Power Detection

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Solution Overview

Problem

In systems-on-chip, programming errors can lead to the master device being blocked when it attempts to access a slave device with a deactivated clock or a powered-off slave device, requiring system restarts.

Innovation Solution

A system-on-chip configuration that includes a master device, slave devices, a clock, and a clock controller, with a control system to detect deactivated clocks or powered-off slave devices, activating the clock or powering on the slave device as needed to prevent blocking, allowing the master device to emit a new access request.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If the clock is deactivated or the slave device is powered off to reduce power consumption, then energy savings are achieved, but the master device may be blocked when it emits an access request to the slave device

Engineering Contradiction:
Improvepower consumptionVSAvoidaccess reliability
Core Design Contradiction:
Use of energy by moving objectVSReliability

Solution Approach 1:

The control system performs preliminary detection of the clock and slave device state before the master device emits an access request. If the clock is deactivated or the slave device is powered off, the control system proactively activates the clock and/or powers on the slave device in advance, preventing the master device from being blocked when it subsequently emits an access request.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If the master device waits for a response from the slave device after emitting an access request, then correct transaction protocol is maintained, but the master device code execution is suspended

Engineering Contradiction:
Improvetransaction correctnessVSAvoidcode execution speed
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The control system continuously monitors the state of clocks and slave devices and provides feedback to the master device. When the master device emits an access request, the control system detects whether the target slave device is ready (clock active and powered on) and either allows the transaction to proceed or triggers preliminary activation, thereby maintaining protocol correctness while minimizing suspension time.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS11907156B2System on a chip and a power down process for IP access resilience
Publication Date: 2024.02.20 STMICROELECTRONICS FRANCE
  • US11907156B2 patent drawing
  • US11907156B2 patent drawing
  • US11907156B2 patent drawing

AI summary

According to one aspect, provision is made of a system-on-chip comprising a master device, a slave device, a clock configured to clock the operation of the slave device, a clock controller configured to activate or deactivate the clock and/or a power-on controller configured to power on/off the slave device, a control system configured to detect that the clock is deactivated and/or that the slave device is powered off when the master device emits an access request to the slave device, the master device being configured for activating the clock when the control system detects that this clock is deactivated and/or powering on the slave device when the control system detects that the slave device is powered off, then emitting a new access request to the slave device.