SoC Master Interface Data Encoding for Power Reduction
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Solution Overview
Problem
As SoC integration and operational speed increase, power consumption also rises, leading to higher chip temperatures and potential inoperability or damage, necessitating improved low-power design methods.
Innovation Solution
The system on chip (SoC) improves clock gating efficiency by reflecting data pattern characteristics before and after data processing, and enhances power consumption efficiency of all flip-flops in the data channel through encoding and decoding operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If SoC integration and operational speed are increased, then functional capability and processing performance are improved, but power consumption increases leading to higher chip temperatures and potential damage
Solution Approach 1:
The master interface performs bit operations and encoding on data before it is transmitted through the data channel. By preprocessing the data (performing bit operations with previous data and encoding the result), the system prepares data in advance to reduce subsequent processing requirements at the slave interface, thereby reducing overall power consumption while maintaining high operational speed
Solution Approach 2:
The system changes the state of data by performing bit operations (XOR, AND, OR) and encoding transformations. The master interface modifies data parameters (performing bit operations on first data and second data, then encoding) before transmission, and the slave interface reverses these changes through corresponding decoding operations, reducing the processing burden and power consumption at the slave end
2Use of energy by moving object
If clock gating technology is applied to bus interface, then power consumption is reduced by reducing device operations, but clock gating efficiency is insufficient without considering data pattern characteristics
Solution Approach 1:
The clock gating circuit uses feedback from data pattern analysis to dynamically control clock signals. The master interface analyzes data patterns (performing bit operations and encoding) and this information feeds back to the clock gating circuit, which adjusts clock signal distribution based on the encoded data patterns, thereby improving clock gating efficiency while maintaining reliability
Solution Approach 2:
The clock gating circuit dynamically adjusts its operation based on data patterns. Instead of static clock gating, the system dynamically controls clock signals to flip-flops based on the encoded data patterns from the master interface, allowing the clock gating efficiency to adapt to varying data characteristics and maintain high reliability across different operating conditions
3Use of energy by moving object
If encoding and decoding operations are implemented, then power consumption efficiency of flip-flops is improved, but device complexity increases
Solution Approach 1:
The encoding and decoding functions are merged into the interface circuits between master and slave devices. The master interface combines bit operation logic and encoding functionality, while the slave interface combines decoding and data processing. This merging approach reduces overall system complexity compared to having separate encoding/decoding modules, while still achieving improved power consumption efficiency through reduced flip-flop operations
Data Source
AI summary
A system on chip is provided. The system on chip includes a bus including a data channel through which data is transmitted in at least one direction and a master interface configured to receive first data from the data channel, perform a bit operation on the first data and on second data input before input of the first data, determine an encoding operation for the first data based on a result of the bit operation, perform the encoding operation on the first data, to obtain encoded data, and provide the encoded data and a transformation signal indicating the encoding operation to the data channel.