SoC MCE Data Export via Network Interfaces With Low-Latency Reporting
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Solution Overview
Problem
Current processor architectures face challenges in efficiently reporting machine check exceptions (MCEs) due to susceptibility of networking stack software and SoCs to crashes, leading to non-operational systems and significant latency when communicating MCEs to remote servers, especially in platforms without an on-board Baseboard Management Controller (BMC) chip.
Innovation Solution
An apparatus and method for exporting MCE data through System-on-Chip (SoC) network interfaces, utilizing a client-server model with a simplified networking stack to directly transmit MCEs to a remote monitoring-server, reducing latency and system downtime.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a complex networking stack is used to transmit MCEs to remote servers, then MCE reporting functionality is achieved, but system reliability deteriorates due to susceptibility to crashes
Solution Approach 1:
The patent extracts the essential MCE transmission functionality from the complex networking stack, implementing only the minimal required communication protocol through the I2C interface to the BMC. This removes the problematic complex networking stack while retaining the core error reporting capability, thereby improving reliability without sacrificing functionality.
Solution Approach 2:
The system is segmented into distinct functional components: the SoC handles MCE detection and generates I2C messages, while the BMC handles remote server communication. This segmentation isolates the critical error detection function from the unreliable networking stack, allowing the SoC to operate independently using the simpler I2C protocol.
2Loss of time
If MCE handlers read and communicate MCEs to remote servers through the networking stack, then error reporting is achieved, but latency increases significantly
Solution Approach 1:
The patent implements preliminary action by enabling the SoC to directly generate and transmit MCE information to the BMC via I2C as soon as an error is detected, without waiting for the networking stack to process and route the information. This preliminary direct transmission significantly reduces the time loss between error occurrence and remote server notification.
3Stability of the object's composition
If the networking stack software and SoCs are made resilient to crashes, then system stability improves, but complexity of the software increases
Solution Approach 1:
The patent employs a lightweight, simple I2C communication protocol that acts as a disposable, stateless communication mechanism between the SoC and BMC. This simple protocol does not require complex software layers or state management, providing stable communication without increasing software complexity. The I2C interface serves as a simple, reliable transport that can be implemented with minimal software overhead.
Data Source
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AI summary
Techniques are described for efficiently and reliably managing machine check exceptions. For example, one embodiment of a processor comprises: a plurality of cores to execute instructions; a plurality of machine check architecture (MCA) banks coupled to the plurality of cores, each MCA bank comprising a plurality of MCA registers to store machine check data (MCD); MCD transmission circuitry to transmit a packet to an error monitoring server, the MCD transmission circuitry to generate a header of the packet using header information stored in one or more packet configuration registers and to generate a payload of the packet using at least a portion of the MCD stored in one or more of the MCA registers.