System-on-Chip Design Modeling Communications as Memory Accesses
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Traditional system-on-chip (SOC) design methodologies are complex and time-consuming due to the need for lower-level descriptions of interconnects and compliance with bus protocols, leading to late detection of errors and significant design delays.
Innovation Solution
The method involves receiving processing modules representing processing units in software, modeling communications as memory accesses, and generating a coherent memory module to represent the memory system, allowing for software-based testing and reduction of design complexity and time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional bus protocols and interconnect systems are used for SOC design, then processing units can communicate through standardized interfaces, but the design complexity and time increase significantly
Solution Approach 1:
The patent creates a software model that copies and simulates the behavior of the complex bus protocol and interconnect system. Instead of implementing the full protocol complexity in hardware design, a simplified software representation captures the essential communication patterns, allowing designers to verify functionality without dealing with the complete protocol complexity.
Solution Approach 2:
The software model acts as an intermediary between the processing units and the actual hardware implementation. It provides a middle layer that abstracts the complex interconnect behavior, allowing processors to be designed and tested independently before final hardware integration, thus reducing overall design complexity.
2Productivity
If traditional bus protocols with DMA controllers are used, then data can be moved between processing units and memory, but the communication path becomes complex and verification is delayed
Solution Approach 1:
The patent enables preliminary functional verification of processor designs by implementing software models of the communication infrastructure. Designers can perform validation activities before final hardware implementation, identifying and fixing issues early in the design process rather than during later verification stages.
Solution Approach 2:
A software copy of the memory system and communication protocols is created, allowing realistic data communication scenarios to be tested in software. This copying approach maintains the essential behavior of the actual hardware while enabling earlier and more flexible verification.
3Ease of manufacture
If high-level design descriptions are used for processing units, then design cost is reduced, but functional verification requires expensive acceleration or emulation boxes
Solution Approach 1:
The patent creates software models that copy the behavior of processing units and their communication environment. These models run on standard computing infrastructure, replacing the need for expensive FPGA prototypes or emulation boxes while maintaining the ability to perform comprehensive functional verification.
Solution Approach 2:
The patent substitutes physical hardware verification systems (emulation boxes, FPGA prototypes) with a software-based verification environment. This replacement eliminates the need for specialized expensive hardware while maintaining verification capability through software simulation of the system behavior.
Data Source
AI summary
Aspects may include a method of designing a system-on-chip. The method may include receiving multiple processing modules, each representing in software one of multiple processing units of a system-on-chip. The method may further include modeling communications from one or more of the multiple processing modules as accesses to memory. The method may further include generating a coherent memory module associated with the multiple processing modules based on modeling the communications from the one or more of the multiple processing modules as accesses to memory. The coherent memory module may represent in software a coherent memory associated with the multiple processing units.