SoC Memory Access Path Power Domain Segmentation
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Solution Overview
Problem
In electronic systems where multiple chips share a memory, keeping one chip active to allow another chip to access the memory results in increased power consumption, and switching the first chip to an active state when the second chip requests access decreases response speed.
Innovation Solution
A system-on-chip (SoC) design where the memory access path can be powered on without intervention from the CPU, allowing a second semiconductor device to access the memory even when the CPU is inactive, and using a delay-locked loop (DLL) locking mechanism to enable the interface without CPU intervention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the first chip remains active to allow the second chip to access the memory, then the second chip can access the memory, but power consumption increases
Solution Approach 1:
The first chip is segmented into two independent power domains: the CPU can be powered off while the memory access path remains powered on. This allows the memory interface to serve the second chip independently without requiring the entire first chip to remain active, thus reducing power consumption while maintaining memory access availability.
Solution Approach 2:
Only the specific memory access path components that are needed for the second chip's access are kept powered on, rather than the entire first chip. This localized power management approach maintains the necessary functionality while minimizing energy consumption by keeping only the relevant circuitry active.
2Use of energy by moving object
If the first chip is inactive and the second chip requests memory access, then power consumption is reduced, but response speed decreases due to the time required to switch to active state
Solution Approach 1:
The memory access path is separated from the CPU as an independent power domain. When the second chip needs memory access, only the memory access path needs to be activated, not the entire first chip or CPU. This segmentation enables faster activation since a smaller circuit portion needs to be powered on, improving response speed while maintaining low power consumption when idle.
Solution Approach 2:
The memory access path can be pre-configured to allow rapid activation. By keeping the memory interface circuitry in a low-power ready state rather than fully off, the system can quickly transition to an active state when needed, reducing the wake-up time and improving response speed without requiring the entire CPU to be active.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces power consumption and enhances response speed by allowing the second semiconductor device to access the memory quickly without powering on the entire first semiconductor device, thereby improving system efficiency and performance.
Implementation Method 1
starting delay-locked loop (DLL) locking to generate a clock signal necessary for an interface with the memory device
Data Source
AI summary
An electronic system including a system-on-chip (SoC) providing access to a shared memory via a chip-to-chip link includes a memory device, a first semiconductor device, and a second semiconductor device. The first semiconductor device includes a first central processing unit (CPU) and a memory access path configured to enable access to the memory device. The second semiconductor device is configured to access the memory device via the memory access path of the first semiconductor device. The second semiconductor device is permitted to access the memory device while the memory access path is active and the first CPU is inactive, and the memory access path is configured to become active without intervention of the first CPU.