Memory Address Remapping for SOC Data Transfer Bottlenecks
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Solution Overview
Problem
The existing memory access schemes in integrated circuits with multiple hardware accelerators are inefficient due to the reliance on slow data crossbar switches, which can lead to prolonged processing times for certain applications, and adding a fast bus between hardware processors and system memory controllers would occupy additional layout area.
Innovation Solution
The solution involves logically swapping memory addresses between different memory blocks within the integrated circuit, allowing hardware processors to access system memory directly without using the data crossbar switch, thereby bypassing the slow data transfer path and eliminating the need for a fast bus between hardware processors and system memory controllers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If data crossbar switch is used for memory access, then device complexity is reduced, but processing speed deteriorates
Solution Approach 1:
The patent segments the memory access paths by providing dedicated direct connections from each hardware accelerator to system memory, separating the fast path (direct connection) from the general path (data crossbar switch). This allows critical data transfers to bypass the shared crossbar switch while maintaining the overall segmented architecture.
Solution Approach 2:
The patent introduces memory controllers as intermediary components that manage direct connections between hardware accelerators and system memory. These controllers act as mediators that handle address translation and data transfer, enabling fast access without requiring a full fast bus implementation between all components.
2Speed
If fast bus is added between hardware processors and system memory controllers, then processing speed is improved, but layout area increases
Solution Approach 1:
The patent applies local quality by providing fast direct connections only where needed - specifically from hardware accelerators that require frequent memory access to system memory. Not all components receive this treatment, allowing the design to optimize speed for critical paths while minimizing the area overhead of additional connection infrastructure.
Solution Approach 2:
The patent performs preliminary action by establishing dedicated connection paths during the design phase for specific hardware accelerators that have predictable and frequent memory access patterns. This allows the layout area to be optimized in advance, reserving space for these critical connections while avoiding the need for comprehensive fast bus infrastructure.
3Adaptability or versatility
If data is copied between local memory and system memory, then data availability is improved, but processing time increases
Solution Approach 1:
The patent extracts the data copying operation from the critical processing path by enabling hardware accelerators to directly access system memory when needed. This removes the intermediate copying step through local memory for operations that can tolerate direct system memory access, extracting only the essential data transfer while leaving processing operations intact.
Solution Approach 2:
The patent introduces dynamics by allowing hardware accelerators to dynamically choose between accessing data through local memory or directly from system memory based on the specific operation requirements. This dynamic selection enables the system to optimize between speed (direct access) and data availability (local cache) on a per-operation basis.
Data Source
AI summary
Hardware processors in an SOC integrated circuit logically swapping memories by remapping memory addresses, including tightly coupled and local memories, to enable a sequence of data-processing algorithms to execute more quickly by different hardware processors without having to copy the data between different memories using a relatively slow data crossbar switch. When a memory stores error-correction code (ECC) address information linking stored ECC data with stored user data, the hardware processor dynamically remaps the ECC address information, as needed.