SoC Memory Bridge for Bandwidth Bottlenecks
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Solution Overview
Problem
In discrete graphics systems, the sole path to graphics memory through the compute engine can cause congestion and make it difficult to diagnose issues with low power states, as all traffic must route through this high-bandwidth component, leading to potential delays and inefficiencies in debugging and power management.
Innovation Solution
An alternative memory interconnect path is provided, allowing SoC agents to directly access graphics memory without going through the compute engine, which includes a memory port and memory bridge with arbitration logic to prioritize traffic and support low power states, enabling debugging and power savings by avoiding the need to wake up high-power components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If all traffic routes through the compute engine to access graphics memory, then high bandwidth is achieved, but congestion occurs and debugging becomes difficult
Solution Approach 1:
The patent segments the memory access path into two separate paths: a high-bandwidth path through the compute engine for graphics workloads, and an alternative debug path through the memory bridge for direct memory access. This segmentation allows each path to be optimized for its specific purpose without interfering with the other, resolving the contradiction between achieving high bandwidth and enabling easy debugging.
2Reliability
If the compute engine remains active to handle memory requests, then memory access is maintained, but power consumption increases
Solution Approach 1:
The patent extracts the debug and low-power memory access functionality from the compute engine by providing an alternative path through the memory bridge. This allows the compute engine to be powered down or placed in low-power states while still maintaining the ability to access graphics memory for debugging or essential operations, thus reducing power consumption without sacrificing memory access reliability.
3Device complexity
If a single memory path is used, then device complexity is reduced, but traffic congestion occurs
Solution Approach 1:
The patent adds another dimension to the memory access architecture by introducing a second independent path (through the memory bridge) parallel to the existing compute engine path. This multi-dimensional approach allows simultaneous memory access through multiple paths, eliminating congestion while maintaining relatively simple device complexity through modular design.
Data Source
AI summary
A system comprising a discrete graphics system-on-chip (SoC) to couple to a host processor unit, the SoC comprising a memory bridge comprising a first port to receive requests sent by a compute engine through a first path to the memory; and a second port to receive requests sent by a plurality of agents of the SoC through a second path to the memory.