SoC Memory Bank Clock Generator Segmentation
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Solution Overview
Problem
The existing system on chip (SoC) devices with a common clock generator experience clock path delays due to parasitic losses in wires, leading to performance hampering and varying internal hold margins across memory banks, which complicates signal routing and processing.
Innovation Solution
Implementing a system on chip (SoC) device with dedicated internal clock generators for each memory bank, which generate local internal clock signals, control signals, and clock reset signals based on an external clock and enable signal, minimizing parasitic losses and optimizing signal timing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a common clock generator is used to provide clock signals to all memory banks, then the device complexity is reduced, but clock path delays occur due to parasitic losses in wires affecting performance
Solution Approach 1:
The patent divides the single common clock generator into multiple dedicated clock generators, with each clock generator assigned to specific memory banks. This segmentation eliminates long wire routing and parasitic losses by generating clock signals locally at each memory bank, thereby resolving the contradiction between device complexity and signal timing accuracy.
Solution Approach 2:
The patent implements local clock signal generation at each memory bank through dedicated clock generators. This local quality approach ensures that each memory bank receives optimally timed clock signals without suffering from wire-induced delays, resolving the timing accuracy issue while maintaining manageable device complexity through modular architecture.
2Device complexity
If a common clock signal is routed to all memory banks, then the device complexity is reduced, but varying internal hold margins occur across memory banks requiring more time and effort for closure
Solution Approach 1:
The patent segments the control signal generation by providing dedicated clock generators to different memory bank groups. This allows independent optimization of clock timing for each group, eliminating the varying hold margin issues that plague common clock distributions and significantly easing the closure process.
Solution Approach 2:
The patent enables independent parameter optimization for each memory bank group by using dedicated clock generators. Each clock generator can be tuned to provide optimal clock signals for its associated memory banks, ensuring consistent internal hold margins across all banks and simplifying the manufacturing closure process.
3Productivity
If dedicated clock generators are implemented for each memory bank, then clock path delays are reduced and performance is enhanced, but the device complexity increases
Solution Approach 1:
The patent segments the clock generation function across multiple dedicated generators, each serving specific memory banks. This segmentation reduces clock path delays and improves memory access speed by eliminating wire routing delays, while the modular nature of the segmentation keeps the complexity increase manageable and organized.
Data Source
AI summary
A system on-chip (SoC) device is provided. The SoC device includes an on-chip memory including memory banks, and internal clock generators. Each internal clock generator is coupled to one or more memory banks. Each internal clock generator generates one or more of an internal clock signal, a control signal and a clock reset signal locally for the memory bank to which the internal clock generator is coupled.