SoC Memory ECC Architecture for Faster Partial Writes and Bus Protection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional error correction codes in system-on-chips (SoCs) face issues such as high timing overhead, inefficient handling of partial writes, and neglect of crosstalk effects on long buses, which impact system performance and reliability, especially in mission-critical applications like automotive and medical systems.
Innovation Solution
The implementation of an electronic circuit with a memory circuit, address and data buffers, a control circuit, and error correcting code (ECC) mechanisms that include a multiplexer, comparing circuit, mixer circuit, and dual-ported parity memory to enhance throughput and reduce timing overhead, while also addressing crosstalk issues through Hsiao code-based ECC solutions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional ECC schemes based on Hamming codes are used, then error correction capability is provided, but timing overhead increases and system operating frequency is slowed down
Solution Approach 1:
The memory system is segmented into multiple banks, allowing parallel ECC operations to be performed simultaneously across different banks. This segmentation enables the system to maintain error correction capability while reducing the timing overhead by distributing the ECC processing load across multiple independent units operating in parallel.
Solution Approach 2:
ECC check bits are generated and stored in advance during write operations, and parity information is pre-computed and stored in dedicated parity memory. This preliminary action ensures that when read operations occur, the ECC verification can be performed immediately without adding significant timing overhead, as the necessary correction data is already prepared.
2Loss of time
If pipelining techniques are used to reduce timing overhead, then throughput is improved, but CPU has to defer memory transactions until pipeline stages are cleared
Solution Approach 1:
A dedicated ECC controller acts as an intermediary between the CPU and memory system, managing the pipeline stages and handling ECC operations independently. This intermediary allows the CPU to continue executing memory transactions without deferring, as the ECC controller handles the error correction tasks in parallel, thus maintaining both reduced timing overhead and high throughput.
Solution Approach 2:
The system employs dynamic pipeline management where the ECC controller can adaptively control the flow of data through pipeline stages based on current system conditions. This dynamic approach allows the system to optimize between timing overhead and throughput by adjusting pipeline depth and stage execution timing according to workload characteristics.
3Difficulty of detecting and measuring
If conventional testing methods using ATPG or BIST techniques are used, then fault detection is performed, but crosstalk effects on long buses are ignored
Solution Approach 1:
The testing system performs not only conventional gate-level and cell-level fault detection but also adds specific crosstalk detection capabilities. By implementing additional test patterns and monitoring mechanisms that specifically target crosstalk effects on long buses, the system achieves comprehensive fault detection without ignoring interconnect issues.
Solution Approach 2:
The ECC controller and testing infrastructure are designed with multi-functionality, serving both conventional error correction and crosstalk detection purposes. The same hardware resources are utilized to perform multiple functions including fault detection, crosstalk monitoring, and error correction, providing a unified approach to reliability enhancement.
4Ease of operation
If partial writes are handled using conventional methods, then memory access is performed, but throughput is impacted due to inefficient handling
Solution Approach 1:
The system implements local quality by maintaining write buffers specifically for partial write operations and using address comparison logic to identify which portions of data need updating. This localized optimization allows partial writes to be handled efficiently by only processing the necessary data portions rather than entire memory words, thus improving throughput while maintaining ease of operation.
Solution Approach 2:
Data is pre-buffered in write buffers before actual memory write operations. This preliminary buffering allows the system to prepare partial write data in advance, compare addresses efficiently, and execute writes only when necessary, thereby improving throughput by reducing redundant memory access operations.
Data Source
AI summary
An electronic circuit (200) for use with an accessing circuit (110) that supplies a given address and a partial write data portion and also has dummy cycles. The electronic circuit (200) includes a memory circuit (230) accessible at addresses, an address buffer (410), a data buffer (440) coupled to the memory circuit (230), and a control circuit (246) operable in the dummy cycles to read data from the memory circuit (230) to the data buffer (440) from a next address location in the memory circuit (230) and to store that next address in the address buffer (410). The electronic circuit further includes a multiplexer (430), a comparing circuit (420) responsive to the given address and a stored address in the address buffer (410), to operate the multiplexer (430) to pass data from the data buffer (440) or to pass data from the memory circuit (230) instead; and a mixer circuit (450) operable to put the partial write data portion into the data taken from the selected one of the data buffer (440) or memory circuit (230). Other circuits, devices, systems, processes of operation and processes of manufacture are also disclosed.