3D SoC Memory Stacking on Fanout Package Structures
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Solution Overview
Problem
Current system on chip (SoC) dynamic random access memory (DRAM) packaging technologies are limited to two-part 3D stacking, which restricts the integration of high-density memory systems, leading to increased costs, cycle times, and package heights that are not suitable for space-constrained mobile devices like VR and AR glasses.
Innovation Solution
A three-part 3D stacking method is implemented by mounting a system on chip face down on a fanout package structure, bonding it face to face with functional chips, and adding additional functional chips either back to back via adhesive and wire bonding or face to back via through silicon vias, surrounded by a mold material.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional two-part 3D stacking packaging is used, then the manufacturing process is simpler, but the memory integration density is limited and package height is larger
Solution Approach 1:
The packaging structure is divided into three distinct parts: a first functional chip, a system-on-chip (SoC) mounted face down on a fanout package structure, and a second functional chip mounted on the SoC. This segmentation enables higher memory integration density by allowing independent optimization of each component's function and placement, while the modular approach manages complexity through standardized interfaces between segments.
2Adaptability or versatility
If additional functional chips are added to increase functionality, then the system capabilities are enhanced, but the package height increases
Solution Approach 1:
The patent transitions from traditional planar or two-layer stacking to a three-dimensional three-part stacking architecture. The first functional chip is positioned at the bottom, the SoC is mounted face down in the middle layer on a fanout package structure, and the second functional chip is mounted on top of the SoC. This vertical three-dimensional arrangement enhances system functionality by integrating multiple functional chips while managing package height through optimized stacking and fanout package design.
3Productivity
If high-density memory integration is achieved through multi-part stacking, then the bandwidth and latency are improved, but the manufacturing cost and cycle time increase
Solution Approach 1:
The SoC is pre-mounted face down on the fanout package structure with its active surface facing downward, and the first functional chip is pre-positioned on the fanout package structure before final assembly. This preliminary arrangement of components and pre-established interconnections enables high-density memory integration with improved bandwidth and latency, while the standardized fanout package structure and modular assembly process help control manufacturing costs and cycle times.
Data Source
AI summary
A method may include mounting a system on chip face down on a fanout package structure in a manner that bonds the system on chip face to face with one or more functional chips included in the fanout package structure. The method may also include mounting an additional functional chip on the system on chip and bonding the additional functional chip to the system on chip. Various other methods, systems, and computer-readable media are also disclosed.