Hybrid-Bonded SoC and Memory Stacking With Fan-Out Vias
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving high integration density, miniaturization, and efficient packaging of semiconductor devices, particularly in stacked and bonded configurations, where sophisticated bonding processes are desired to reduce physical size and improve performance.
Innovation Solution
The method involves forming first and second semiconductor devices with specific layers and materials, including substrates, active devices, metallization layers, and conductive bond materials, followed by hybrid bonding and encapsulation, and integrating fan-out vias to create a high-performance, low-cost structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If semiconductor devices are stacked and bonded to achieve high integration density, then integration density is improved, but bonding process complexity increases
Solution Approach 1:
The patent applies preliminary action by forming conductive bond materials and metallization layers on semiconductor devices before the bonding process. This pre-preparation of bonding surfaces and conductive structures simplifies the subsequent bonding operation, allowing for more reliable stacked device integration without increasing process complexity during the actual bonding step.
Solution Approach 2:
The patent uses conductive bond materials as intermediaries between semiconductor devices to be bonded. These conductive materials facilitate both mechanical bonding and electrical connection, simplifying the overall bonding process by combining multiple functions into a single intermediate layer rather than requiring separate bonding and connection steps.
2Quantity of substance
If minimum feature size is reduced to increase integration density, then integration density is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent addresses the limitations of continuing to reduce minimum feature size by transitioning to three-dimensional stacking architectures. Instead of packing more components in two dimensions by shrinking features, the invention vertically stacks semiconductor devices, achieving higher integration density through the third dimension while maintaining manufacturable feature sizes.
Solution Approach 2:
The patent divides the semiconductor integration problem into separate manageable components that are fabricated independently at standard feature sizes, then bonded together in stacks. This segmentation allows each component to be manufactured with conventional precision requirements while the overall system achieves high integration density through the stacked configuration.
3Volume of moving object
If sophisticated bonding techniques are used to reduce physical size, then device size is reduced, but ease of manufacture decreases
Solution Approach 1:
The patent merges the bonding function with the electrical connection function by using conductive bond materials that simultaneously provide mechanical adhesion and electrical conductivity. This consolidation eliminates the need for separate bonding and interconnection processes, reducing physical device size while maintaining ease of manufacture through process integration.
Solution Approach 2:
The conductive bond materials serve multiple functions: mechanical bonding, electrical connection, and potentially thermal management. This multi-functionality reduces the number of separate components and processes needed, achieving compact device size without sacrificing manufacturing simplicity.
Data Source
AI summary
A semiconductor device and method of manufacture are provided wherein the semiconductor device includes a first system on chip device bonded to a first memory device, a second system on chip device bonded to the first memory device, a first encapsulant surrounding the first system on chip device and the second system on chip device, a second encapsulant surrounding the first system on chip device, the second system on chip device, and the first memory device, and a through via extending from a first side of the second encapsulant to a second side of the first encapsulant, the through via being located outside of the first encapsulant.