SoC Memory Interface Logical Bank Configuration
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Solution Overview
Problem
The organization of physical memory banks in system-on-chip (SoC) does not adequately address the needs for flexible storage and update of compiled code, particularly in ensuring a root of trust and allowing for seamless updates without interrupting application execution, especially after power interruptions.
Innovation Solution
A memory interface that stores logical memory bank configuration information in configuration registers, allowing each sector of physical banks to be assigned to logical memory banks, enabling flexible memory access and configuration independent of physical bank organization, with the ability to lock configurations for trust and interchange logical banks for updated code storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If physical memory banks are organized during design with fixed sector assignments, then memory structure is simplified and manufacturing is easier, but flexibility in storing and updating compiled code is reduced
Solution Approach 1:
The memory is divided into multiple physical banks, each independently addressable and controllable. This segmentation allows the system to manage different code storage requirements in different banks, providing both structural simplicity and operational flexibility.
Solution Approach 2:
The patent introduces dynamic bank selection and switching capabilities, where the system can change which physical bank is active for code execution at different times. This allows the same physical memory structure to serve multiple logical purposes, enhancing adaptability without requiring physical reconfiguration.
2Productivity
If memory sectors are erased by sector rather than by bit, then erasure operations are simpler and faster, but the ability to update specific code portions is limited
Solution Approach 1:
Each physical bank is divided into multiple sectors that can be independently erased and programmed. This sector-level organization allows the system to erase only the specific sectors containing code that needs updating, rather than erasing entire banks or requiring bit-level operations.
Solution Approach 2:
The system performs preliminary sector identification and selection before erasure operations. By determining which specific sectors need to be updated and preparing the appropriate sector masks and control signals in advance, the system optimizes the erasure process for both speed and precision.
3Speed
If the processor looks for compiled code at a fixed start-up address, then system initialization is simpler and faster, but the system becomes unusable if no executable code exists at that address
Solution Approach 1:
The patent introduces a memory interface and control logic that act as intermediaries between the processor and physical memory banks. This intermediary layer can dynamically determine the actual location of executable code, translate logical addresses to physical bank addresses, and redirect the processor to the correct code location, maintaining both fast initialization and system reliability.
Solution Approach 2:
The system implements dynamic bank selection and address translation capabilities that allow the start-up address to effectively point to different physical locations depending on where code has been programmed. This dynamic addressing ensures the processor can quickly locate and execute code regardless of its physical storage location.
4Device complexity
If memory banks are physically defined during design, then hardware implementation is simpler, but the organization is not adapted to user needs for code updates and power resilience
Solution Approach 1:
The patent introduces a logical dimension of memory organization that overlays the physical bank structure. By creating logical banks that can span multiple physical banks and implementing logical-to-physical address translation, the system provides flexible memory organization for user needs while maintaining simple physical hardware implementation.
Solution Approach 2:
The memory interface and control logic are designed to handle multiple functions: code storage, data storage, update operations, and power-resilient operations. This universal interface can adapt to different user requirements without requiring changes to the underlying physical bank structure, allowing the same hardware to serve multiple purposes.
Data Source
AI summary
A system-on-chip includes a processor, a memory and a memory interface coupled to the processor and to the memory. The processor, in operation, generates memory access requests. The memory includes one or more physical banks divided into a succession of sectors, each sector having a size equal to a smallest erasable size of the memory. The memory interface, in operation, responds to receiving memory configuration information by storing logical memory bank configuration information in the one or more configuration registers, the logical memory bank configuration information assigning each sector of the one or more physical banks of the memory to a respective logical memory bank of one or more logical memory banks. The memory interface, in operation, controls access to the memory by the processor based on the logical memory bank configuration information stored in the one or more configuration registers.