SoC-Memory Key Binding for Secure Memory Replacement

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Solution Overview

Problem

Existing System-on-a-Chip (SoC) architectures face challenges in securely binding with memory devices due to the limited lifespan of memory devices, which can fail before the SoC, necessitating replacement of both components, leading to inefficiency and increased costs.

Innovation Solution

Implementing multi-key support in SoC architectures that allow for the activation and provisioning of multiple keys, enabling the SoC to bind with replacement memory devices using a new key when the current memory device fails, thereby extending the SoC's operational life without replacing it.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a single key is programmed into the memory device for binding with the SoC, then device security is provided, but the SoC must be replaced when the memory device fails, leading to increased costs and inefficiency

Engineering Contradiction:
Improvedevice securityVSAvoidmemory device replacement capability
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent segments the key storage functionality by implementing multiple separate key locations (first key location, second key location, etc.) within the memory device. Each key location can store a different key, allowing the system to bind with multiple different memory devices sequentially while maintaining security through individual key protection

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent changes the parameter of key diversity by provisioning multiple distinct keys to different key locations in the memory device. The SoC can selectively activate different keys corresponding to different memory devices, enabling the system to adapt to memory device replacements without compromising security

Inventive Principle:
Principle #35Parameter changes

2Reliability

If OTP memory is used for key storage, then security is maintained through one-time programming, but the key cannot be changed or updated, requiring SoC replacement when memory device fails

Engineering Contradiction:
Improvekey securityVSAvoidoperational lifespan
Core Design Contradiction:
ReliabilityVSDuration of action of moving object

Solution Approach 1:

The patent introduces dynamic key management capabilities by enabling the SoC to provision multiple keys to different key locations and selectively activate different keys based on which memory device is currently in use. This dynamic key switching allows the system to extend its operational lifespan by replacing memory devices while maintaining security through appropriate key activation

Inventive Principle:
Principle #15Dynamics

3Reliability

If the memory device has a limited lifespan, then hardware replacement is necessary, but replacing both the memory device and SoC leads to resource waste and increased costs

Engineering Contradiction:
Improvememory device functionalityVSAvoidresource utilization
Core Design Contradiction:
ReliabilityVSLoss of substance

Solution Approach 1:

The patent implements multi-functionality in the key storage structure by creating key locations that can serve multiple purposes: storing keys for different memory devices, enabling sequential binding with multiple memory devices over time, and extending the SoC's operational life without requiring SoC replacement. This universal key management approach allows one SoC to work with multiple memory devices throughout its lifetime

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS12566868B2Apparatus and methods for binding a system on chip and a memory device with a key
Publication Date: 2026.03.03 QUALCOMM INC
  • US12566868B2 patent drawing
  • US12566868B2 patent drawing
  • US12566868B2 patent drawing

AI summary

Methods and apparatuses directed to providing multi-key support within die architectures, such as System-on-a-Chips. In some examples, a die package includes key activation fuses, key revocation fuses, and key fuses for multiple keys. The die package also includes a processor electrically coupled to the key activation fuses, the key revocation fuses, and the plurality of key fuses. Further, the processor can generate a first key value and write the first key value to the key fuses to generate a first key. The processor can also write to the key activation fuses to activate the first key. The processor can further provision the first key to a first memory device. When the first memory device is replaced with a second memory device, the processor can write to the key revocation fuses to revoke the first key, and can provision a second key to the second memory device.