Three-Part SoC Memory Stacking for Low-Profile Mobile Packaging
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Solution Overview
Problem
Current system on chip (SoC) dynamic random access memory (DRAM) packaging technologies are limited to two-part 3D stacking, which does not meet the form factor requirements for space-constrained mobile devices like virtual reality (VR) headsets and augmented reality (AR) glasses, and are costly and time-consuming.
Innovation Solution
Implementing a three-part system on chip memory stacking by positioning a packaging laminate substrate between a system on chip and a functional chip, connecting them via a via stack, mounting an additional functional chip back-to-back with an adhesive, and bonding it with wire bonding, which includes a via stack with specific pitch and size configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If two-part 3D stacking is used for SoC-DRAM packaging, then the packaging process is simpler, but the package height is too large for space-constrained mobile devices
Solution Approach 1:
The packaging structure is segmented into three distinct parts: a system on chip (SoC), a functional chip (FC), and an additional functional chip (AFC) mounted back-to-back on the SoC. This segmentation allows the memory components to be distributed across multiple chips rather than requiring a single tall stack, thereby reducing overall package height while maintaining functionality
Solution Approach 2:
The patent transitions from vertical stacking (single dimension) to a combination of vertical and lateral arrangements. The additional functional chip is mounted back-to-back on the SoC in the lateral direction, and then bonded to the functional chip through wire bonding. This dimensional change allows memory capacity expansion without increasing package height significantly
2Productivity
If traditional two-part 3D stacking is used, then manufacturing is easier, but cost and cycle time are high
Solution Approach 1:
The additional functional chip is mounted back-to-back on the system on chip before bonding to the functional chip. This preliminary arrangement of components allows for optimized wire bonding paths and reduces the number of separate bonding operations required, thereby reducing manufacturing cycle time
Solution Approach 2:
Wire bonds serve as intermediaries connecting the additional functional chip to the functional chip. This intermediary connection method allows for flexible routing and connection establishment after the chips are positioned, enabling more efficient manufacturing processes compared to requiring precise pre-alignment of all components
Data Source
AI summary
A method for three part system on chip memory stacking may include positioning a packaging laminate substrate between a system on chip and a functional chip, wherein the functional chip is connected to the system on chip by a via stack included in the packaging laminate substrate. The method may also include mounting an additional functional chip on the system on chip and bonding the additional functional chip to the system on chip. Various other methods, systems, and computer-readable media are also disclosed.