SoC Memory Access Control for PDN Resonance Mitigation
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Solution Overview
Problem
Resonance in the power distribution network (PDN) of a system-on-chip (SoC) memory subsystem due to inductive and capacitive effects, leading to performance degradation and failures, which existing methods to mitigate resonance, such as adding decoupling capacitors, are costly and inefficient.
Innovation Solution
Implementing resonance mitigation control logic in the memory controller to monitor and break repeated memory access patterns by introducing idle periods when an accumulated value reaches a threshold, reducing the need for additional decoupling capacitors and minimizing noise in the PDN.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If decoupling capacitors are added to mitigate resonance in the PDN, then resonance-induced noise is reduced, but device complexity and cost increase
Solution Approach 1:
The patent replaces the physical approach of adding decoupling capacitors (hardware modification) with a software-based solution that uses processing logic to detect and modify memory access patterns. The control logic monitors access patterns, calculates accumulated values, and introduces idle periods to break resonance-causing patterns, thereby substituting hardware mitigation with intelligent control software.
Solution Approach 2:
The patent changes the temporal parameters of memory access patterns by dynamically introducing idle periods between access operations. By modifying the timing and frequency characteristics of memory accesses based on calculated accumulated values, the system shifts the operating frequency away from resonance peaks without adding physical components.
2Object-affected harmful factors
If decoupling capacitors are added to mitigate resonance, then noise is reduced, but manufacturing cost increases
Solution Approach 1:
The patent employs software-based control logic that is already present in the memory controller, eliminating the need for additional expensive decoupling capacitors. The processing logic uses existing hardware resources and software algorithms to achieve noise mitigation, thereby reducing manufacturing costs while maintaining effectiveness.
3Object-affected harmful factors
If memory access patterns are modified to break resonance, then noise is reduced, but productivity decreases
Solution Approach 1:
The patent applies partial modification to memory access patterns by only introducing idle periods when the accumulated value exceeds a threshold, rather than continuously modifying all access patterns. This selective approach breaks resonance-causing patterns while maintaining normal high-speed operation during non-resonant periods, thereby minimizing impact on productivity.
Solution Approach 2:
The patent uses periodic monitoring of memory access patterns and calculates accumulated values at regular intervals. By applying periodic control actions (introducing idle periods) only when resonance conditions are detected, the system maintains normal operation during non-resonant periods while effectively mitigating noise when needed.
Data Source
AI summary
A processing device identifies a repeated memory access pattern in a memory access stream of a memory subsystem, the repeated memory access pattern having a memory access pattern frequency, and determines an accumulated value associated with the repeated memory access pattern. The processing device further determines whether the accumulated value satisfies a threshold criterion associated with the memory access pattern frequency, and responsive to determining that the accumulated value satisfies the threshold criterion, causes a delay period to be introduced to the memory access stream to break the repeated memory access pattern.