SoC Memory Management System Asynchronous Reset Protection
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Solution Overview
Problem
In system-on-chip (SoC) devices, asynchronous reset events lead to memory corruption and significant reinitialization times, causing unreliable behavior and degradation in reliability and accuracy due to delayed fault reactions and faulty component operation.
Innovation Solution
A memory management system utilizing flip-flops and logic gates is introduced between the memory controller and system memory, controlling memory operations to prevent corruption by executing read and write operations in a specific sequence, allowing instantaneous asynchronous reset signal provision without delaying memory controller resets.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If asynchronous reset signal is delayed until system memory transitions to default state, then memory corruption is avoided, but fault reaction time is delayed and functional components operate in faulty condition
Solution Approach 1:
The reset signal distribution is segmented into two independent paths: one path goes to the memory controller with immediate effect, and another path goes through the memory management system which controls when the memory is actually reset. This segmentation allows the memory controller to be reset immediately for fast fault reaction while the memory itself is protected during the reset transition.
Solution Approach 2:
The memory management system acts as an intermediary between the reset signal source and the system memory. It receives the reset signal and controls its propagation to the memory based on the current operation state, thereby protecting memory integrity while allowing immediate reset of other components.
2Loss of time
If asynchronous reset signal is provided immediately to memory controller, then fault reaction time is reduced, but memory corruption occurs requiring reinitialization
Solution Approach 1:
The reset signal distribution is segmented into two independent paths: one path goes to the memory controller with immediate effect, and another path goes through the memory management system which controls when the memory is actually reset. This segmentation allows the memory controller to be reset immediately for fast fault reaction while the memory itself is protected during the reset transition.
Solution Approach 2:
The memory management system performs preliminary detection of the reset signal and determines whether the memory is currently in a vulnerable state before allowing the reset to propagate. This preliminary action prevents memory corruption while still allowing immediate reset of the memory controller.
3Reliability
If system memory is reinitialized after each asynchronous reset, then memory corruption is corrected, but significant time is lost during reinitialization
Solution Approach 1:
The memory management system provides beforehand protection by detecting reset signals in advance and preventing them from reaching the memory during vulnerable states. This cushioning effect avoids memory corruption in the first place, eliminating the need for time-consuming reinitialization operations.
4Loss of time
If functional components continue operating during delayed reset signal, then fault detection is maintained, but unreliable behavior and degradation in accuracy occur
Solution Approach 1:
The reset signal distribution is segmented into two independent paths: one path goes to the memory controller with immediate effect, and another path goes through the memory management system which controls when the memory is actually reset. This segmentation allows the memory controller to be reset immediately for fast fault reaction while the memory itself is protected during the reset transition.
Data Source
AI summary
A system-on-chip (SoC) includes a system memory, a memory controller, and a memory management system coupled therebetween. The memory management system is configured to receive, from the memory controller, a first control signal that is indicative of a memory operation associated with the system memory, and output and provide a second control signal to the system memory to control an execution of the memory operation. The second control signal is outputted such that when the memory operation corresponds to a first read operation, the first read operation is executed with the system memory, and when the memory operation corresponds to a first write operation, a second read operation is executed with the system memory followed by the first write operation. Thus, the memory management system prevents memory corruption of the system memory when an asynchronous reset event is detected in the SoC.