SoC Read/Write Sequencing Across Strict and Relaxed Memory Models
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Solution Overview
Problem
Existing systems face challenges in optimizing transmission bandwidth and interaction efficiency between nodes with different memory consistency models, particularly when a node complying with a strict order constraint needs to perform read/write operations in a relax order model, leading to reduced efficiency and scalability.
Innovation Solution
A read/write operation execution method where a first node receives messages from a second node with stricter execution constraints, obtains permission for addresses from a third node with relaxed constraints, and performs operations in parallel, extending the cache coherence domain to ensure globally observable execution results meet strict order requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a node with strict order constraint performs read/write operations in a relax order model, then the execution sequence strictness is reduced, but the transmission bandwidth and interaction efficiency are improved
Solution Approach 1:
The patent introduces a first node as an intermediary between the second node (strict order model) and the third node (relax order model). This intermediary translates and coordinates read/write requests, allowing the second node to maintain its strict ordering requirements while the third node operates under relaxed ordering, thereby resolving the contradiction between execution sequence strictness and interaction efficiency
Solution Approach 2:
The system segments the memory access path into distinct functional nodes: the second node (SO model), the first node (intermediary), and the third node (RO model). Each segment handles specific aspects of the read/write operations, allowing independent optimization of ordering strictness and transmission efficiency in different segments simultaneously
2Productivity
If parallel processing is implemented across different memory consistency models, then transmission bandwidth is improved, but the complexity of managing execution sequences increases
Solution Approach 1:
The first node serves as a mediator that manages the complexity of coordinating parallel operations between nodes with different memory consistency models. It tracks and reconciles execution sequences, allowing parallel processing to proceed while maintaining correctness, thus reducing the burden on individual nodes and overall system complexity
3Adaptability or versatility
If a first node is introduced to extend cache coherence domain, then scalability is improved, but the device complexity increases
Solution Approach 1:
The first node is designed with multi-functionality, serving as both a regular processing node and a cache coherence manager. It handles both data processing tasks and coordination of execution sequences between different memory consistency models, reducing the need for additional specialized components and thereby limiting the increase in overall device complexity while improving scalability
Data Source
AI summary
This application discloses a read/write operation execution method and a SoC chip. The read/write operation execution method includes: A first node receives a first message and a second message from a second node, where the first message is for requesting to perform a read/write operation on a first address managed by a third node, the second message is for requesting to perform a read/write operation on a second address managed by the third node, an execution sequence constraint of the read/write operation of the second node is stricter than an execution sequence constraint of the read/write operation of the third node; the first node obtains operation permission of the first address and operation permission of the second address from the third node; and the first node performs read/write operations on the first address and the second address.