SoC Memory Sharing for Compact Multi-Processor Boot
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Solution Overview
Problem
The integration of multiple processors on a single semiconductor substrate for electronic devices, such as smartphones, is limited by the need for dedicated non-volatile and volatile memories for each processor, restricting the number of processors that can be included without increasing the physical size of the System-on-Chip (SoC).
Innovation Solution
A System-on-Chip (SoC) design that includes a non-volatile memory for storing boot loaders and firmware images, a volatile memory with multiple areas for secure and shared access, and processors configured to perform boot operations and integrity verification, allowing for efficient memory sharing and secure data handling while maintaining a compact size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If each processor is provided with dedicated non-volatile memory and volatile memory, then each processor can independently store boot loader and firmware data, but the physical size of the SoC increases and the number of processors that can be included is limited
Solution Approach 1:
The patent merges the memory resources for multiple processors by implementing a shared volatile memory structure with different access modes. The volatile memory is divided into a first area accessible by both processors and a second area accessible only by the application processor. This consolidation eliminates the need for separate dedicated memories for each processor, thereby reducing the overall SoC physical size while maintaining independent boot capabilities through the shared memory architecture.
Solution Approach 2:
The volatile memory is designed with multi-functional access capabilities where the first area can be accessed by both the application processor and communication processor, while the second area is exclusively accessible by the application processor. This universal memory design allows a single memory structure to serve multiple processors for their respective boot operations, eliminating the need for separate dedicated memory blocks and reducing SoC footprint.
2Reliability
If separate non-volatile memories are provided for each processor, then each processor has dedicated storage for boot loader and firmware, but the device complexity increases
Solution Approach 1:
The patent combines the non-volatile memory resources into a single shared structure that stores boot loader and firmware images for both processors. The application processor is configured to copy the boot loader and firmware image from this shared non-volatile memory to the volatile memory first area before executing the communication processor's boot operation. This merging approach reduces device complexity by eliminating multiple separate non-volatile memory blocks while maintaining firmware integrity through the copy-and-verify mechanism.
Solution Approach 2:
The application processor performs a preliminary action by copying the boot loader and firmware image from the shared non-volatile memory to the volatile memory first area before the communication processor executes its boot operation. This preliminary copy operation ensures that the communication processor can independently access the firmware data in the volatile memory without requiring direct access to the non-volatile memory, thereby simplifying the overall memory access architecture while maintaining security and integrity.
3Area of stationary object
If volatile memory is shared between processors with different access rights, then memory space is optimized, but secure data handling becomes more complex
Solution Approach 1:
The volatile memory is segmented into two distinct areas with different access characteristics: a first area that can be accessed by both the application processor and communication processor, and a second area that is exclusively accessible by the application processor. This segmentation allows efficient memory space utilization while maintaining clear access boundaries that simplify the security management mechanism, as each area has well-defined access rights rather than requiring complex permission checks across the entire memory space.
Data Source
AI summary
A system-on-chip (SoC) includes an application processor (AP) including a secure module and a non-secure module, a communication processor (CP), a volatile memory having a first area accessible by the CP, a second area accessible by only the AP, and a third area accessible by the CP and the AP, and non-volatile memory storing a boot loader and a firmware image. Upon power-up of the SoC, the AP copies the boot loader and firmware image from the non-volatile memory to the first area using the non-secure module, switches the first area from a normal mode to a secure mode using the secure module, and verifies integrity of the first firmware image to activate a reset signal. The CP then performs a CP boot operation using the boot loader and firmware image stored in the first area in response to the activated reset signal.