Universal SOC Architecture for Flexible Memory Stacking
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Solution Overview
Problem
Current semiconductor devices require separate design of system-on-chip (SOC) for different bandwidths and integration densities due to the need to expand the region for through-silicon vias (TSVs) when increasing the number of wide input/output memory devices, limiting flexibility and efficiency.
Innovation Solution
A semiconductor device architecture that allows for the stacking of multiple wide input/output memory devices with varying densities and bandwidths on a system-on-chip (SOC) with a predetermined TSV region, using independent input/output channels, memory controllers, a clock signal generator, and a central processing unit to manage data transmission and clock signal frequencies, enabling flexible data communication through memory bumps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of wide input/output memory devices is increased to expand bandwidth or integration density, then memory bandwidth and integration density are improved, but the region for through-silicon vias must be expanded requiring separate SOC designs for each configuration
Solution Approach 1:
The patent implements a universal SOC design with a standardized TSV region that can support any number of wide input/output memory devices (one, two, or more) stacked thereon. The SOC includes a plurality of input/output channels and memory controllers that can be flexibly configured to work with different numbers and types of memory devices, eliminating the need for separate SOC designs for different bandwidth or density requirements.
Solution Approach 2:
The patent employs dynamic configuration capabilities where the clock signal generator can produce clock signals of various frequencies, and the central processing unit can set the clock frequency in accordance with the number of stacked memory devices. This dynamic adjustment allows the same SOC to adapt to different memory configurations and performance requirements without requiring separate designs.
2Reliability
If separate SOC designs are created for different bandwidths and integration densities, then specific performance requirements are met, but manufacturing complexity and design time increase
Solution Approach 1:
The patent creates a single universal SOC design that can be manufactured once and used for multiple applications with different bandwidth and density requirements. The standardized TSV region and flexible memory controller configuration enable this one SOC design to serve multiple purposes, significantly reducing manufacturing complexity and design time compared to creating separate designs for each specification.
Solution Approach 2:
The patent allows performance optimization through parameter changes rather than design changes. The clock signal generator can produce various frequencies, and the CPU can adjust operational parameters based on the number of stacked memory devices, enabling the same manufactured SOC to meet different performance specifications through configurable parameters.
3Quantity of substance
If the TSV region is expanded to accommodate more memory devices, then integration density is improved, but the SOC design must be customized for each configuration
Solution Approach 1:
The patent defines a standardized TSV region in the SOC design that can accommodate one, two, or more wide input/output memory devices stacked thereon. This universal TSV region design eliminates the need to expand or customize the TSV region for different configurations, as the same standardized region supports varying integration densities through stacking rather than lateral expansion.
Data Source
AI summary
A semiconductor device includes a system-on-chip (SOC) and at least one wide input/output memory device. The SOC includes a plurality of SOC bump groups which provide input/output channels, respectively, independent from each other. The at least one wide input/output memory device is stacked on the system-on-chip to transmit/receive data to/from the system-on-chip through the SOC bump groups. The SOC bump groups are arranged and the at least one wide input/output memory device is configured such that one of the wide input/output memory devices can be mounted to the SOC as connected to all of the SOC bump groups, or such that two wide input/output memory devices can be mounted to the SOC with each of the wide input/out memory devices connected a respective half of the SOC bump groups.