SoC Memory Interface Timing Training for VT Delay Compensation
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Solution Overview
Problem
Existing system-on-chip (SoC) data training on memory devices is limited by access restrictions, leading to performance deterioration due to internal memory device characteristics, particularly VT variation, which increases training time and reduces system efficiency.
Innovation Solution
The SoC employs a control logic circuit to sequentially transmit data with varying delay times based on a pre-stored edge code, followed by continuous read commands to determine and compensate for delay values, minimizing training time by optimizing write and read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the SoC performs data training on the memory device to compensate for delay due to VT variation, then the delay compensation is achieved, but the access to the memory device is limited and the performance of the memory system deteriorates
Solution Approach 1:
The patent performs data training operations before normal memory access operations to pre-compensate for delay variations. By conducting the training sequence in advance, the system establishes optimal timing parameters that will be used during subsequent normal operations, thus achieving reliable delay compensation without repeatedly limiting access during regular operation.
Solution Approach 2:
The patent implements periodic data training sequences at specific intervals or under specific conditions (such as temperature changes or voltage variations). This periodic approach allows the system to maintain delay compensation while minimizing the frequency and duration of access limitations, thereby balancing reliability with overall system productivity.
2Measurement precision
If the SoC sequentially transmits pieces of first data with different delay times to the memory device, then the delay measurement precision is improved, but the time required for data training increases
Solution Approach 1:
The patent segments the data training process into multiple phases: an initial coarse measurement phase that quickly identifies the approximate delay range, followed by a fine measurement phase that precisely determines the actual delay value. This segmentation allows the system to achieve high measurement precision without requiring the full time budget for all measurement iterations, as the coarse phase narrows down the search space.
Solution Approach 2:
The patent transmits a plurality of pieces of first data with different delay times, which is more than the single data transmission that would be minimally required. This excessive action provides redundant measurements that improve delay measurement precision through statistical analysis or pattern recognition, while the system optimizes the number of transmissions to avoid excessive training time.
Data Source
AI summary
Disclosed is a SoC. The SoC communicating with a memory device includes a memory interface that exchanges a command and data with the memory device, and a control logic circuit that transmits a clock signal and a plurality of data signals to the memory device through the memory interface. The control logic circuit sequentially transmits pieces of first data with different delay times to the memory device through the memory interface based on a pre-stored first edge code, continuously transmits, to the memory device, a plurality of read commands for reading the pieces of first data stored in the memory device from the memory device, and obtains a first delay value including an extent, to which the pieces of first data are delayed, based on a data pattern of each of pieces of first reception data read from the memory device in response to the plurality of read commands.