SoC Memory Training with Simultaneous Duty Cycle and Vref Tuning
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Solution Overview
Problem
The existing system on chip (SoC) technologies face suboptimal results in training processes due to the dependency and order of operations among ZQ calibration, reference voltage training, read training, and clock duty cycle training, which affect the performance of data input/output signals and clock duty cycles when communicating with memory devices.
Innovation Solution
The SoC includes a clock generator, reference voltage generator, data receiver, and processor that adjust the clock duty cycle and reference voltage levels simultaneously, align data strobe and input/output signals, and calculate read valid window margins for various code combinations to optimize training outcomes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple trainings are performed in sequence with dependency on each other, then the training process can be completed with traditional methods, but the training results are suboptimal and non-preferred
Solution Approach 1:
The patent performs preliminary actions by simultaneously adjusting multiple parameters (clock duty cycle, reference voltage level, data strobe signal alignment) before conducting the actual training. This allows all dependent trainings to be performed with optimal parameters from the start, rather than sequentially adjusting one parameter at a time and re-training multiple times.
Solution Approach 2:
The patent merges multiple independent training adjustments into a single simultaneous operation. Instead of performing ZQ calibration, reference voltage training, read training, and clock duty cycle training in separate sequential steps, the system adjusts all parameters concurrently to achieve optimal training results in one process.
2Reliability
If multiple trainings are performed simultaneously with independent parameter adjustments, then optimal training results can be achieved, but the control and measurement complexity increases
Solution Approach 1:
The patent implements feedback mechanisms where the system calculates read valid window margins based on multiple combinations of parameter values, identifies the optimal combination that maximizes the margin, and then sets the parameters accordingly. This feedback loop ensures reliable communication while systematically managing the complexity of multiple parameter adjustments.
Solution Approach 2:
The patent systematically changes parameters (first code for clock duty cycle, second code for reference voltage level) through multiple combinations and evaluates each combination's effect on read valid window margin. This methodical parameter exploration allows the system to find optimal settings for reliable communication while managing the complexity through structured evaluation.
Data Source
AI summary
A system on chip includes a clock generator that adjusts a duty cycle of a clock to be output to a memory device depending on a first code, a reference voltage generator that adjusts a level of a reference voltage used to determine a first data input/output signal output from the memory device depending on a second code, a data receiver that aligns a first data strobe signal and the first data input/output signal output from the memory device, when one of the first code and the second code is changed, and a training circuit that calculates a plurality of read valid window margins for a plurality of combinations of the first code and the second code based on the first data strobe signal and the first data input/output signal.