SoC Memory World Identifier Checks for Secure Error Isolation
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Solution Overview
Problem
Existing software isolation mechanisms fail to provide robust security and safety guarantees in systems on a chip, as they either prioritize security over safety or vice versa, leading to potential interference between software applications sharing resources, which can compromise critical systems like medical devices or security systems.
Innovation Solution
Implementing a hardware-enforced multi-domain solution, such as SiFive WorldGuard, which creates distinct 'worlds' for software applications, ensuring strict isolation through world identifiers and access control mechanisms, including wgMarkers and wgCheckers, to manage and enforce access rules, and a trusted world processor core for error management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If software isolation mechanisms are implemented to prevent interference between applications, then security and safety are improved, but device complexity increases
Solution Approach 1:
The patent divides the memory space into separate memory regions (first memory region and second memory region) with distinct access control mechanisms. Each region has its own set of world identifiers and access rules, creating segmentation that isolates applications while maintaining manageable complexity through hardware-supported region separation.
Solution Approach 2:
The patent introduces a memory controller as an intermediary component that mediates between applications and memory regions. The memory controller enforces access control policies by checking world identifiers against authorized lists before allowing memory access, thereby providing isolation without requiring complex software-level mechanisms.
2Reliability
If hardware-enforced isolation is implemented to prevent unauthorized access, then security is improved, but ease of operation deteriorates
Solution Approach 1:
The patent implements self-service by having the memory controller automatically enforce access control policies based on pre-configured world identifiers and authorized lists. Applications simply need to provide their world identifier with memory requests, and the hardware automatically determines whether access is permitted without requiring manual intervention or complex operation.
Solution Approach 2:
The patent uses parameter changes by dynamically selecting and validating world identifiers associated with different memory regions. The system changes the access control parameters (authorized world identifier lists) based on the specific memory region being accessed, allowing flexible security policies without complicating the basic memory access operation.
3Adaptability or versatility
If multiple memory regions with different access control are implemented, then adaptability is improved, but device complexity increases
Solution Approach 1:
The patent achieves universality by implementing a single memory controller that handles access control for multiple memory regions with different access policies. The memory controller uses a unified approach (checking world identifiers against authorized lists) that works across all regions, providing adaptability without proportionally increasing complexity.
Solution Approach 2:
The patent adds a dimension to memory access by introducing world identifiers as an additional parameter alongside traditional memory addresses. This dimensional extension allows the system to differentiate between multiple memory regions and applications without fundamentally changing the basic memory access mechanism, thereby improving adaptability while managing complexity.
Data Source
AI summary
Systems and methods are disclosed for error management in a system on a chip with a securely partitioned memory space. For example, an integrated circuit (e.g., a processor) for executing instructions includes a world identifier checker circuitry configured to check memory requests for one or more memory mapped resources that are received via the bus that have been tagged with a world identifier to determine whether to allow or reject access based on the tagged world identifier; a world identifier checker circuitry configured to compare the tagged world identifier to a world list for a resource that specifies which world identifiers supported by the integrated circuit are authorized for access to the resource; and a data store configured to store world error data, including the tagged world identifier of a memory request that has been rejected by the world identifier checker circuitry.