SoC Interconnect Message Packing for Higher Bandwidth
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Solution Overview
Problem
Existing communication methods in System-on-Chip (SoC) circuits are inefficient, leading to reduced bandwidth due to unused bits and increased complexity in logic, especially when messages span multiple clock cycles or are shorter than the data bus width.
Innovation Solution
A method and system for transmitting contiguous messages with an integrated circuit, using a three-bit logical signal to indicate the end of a message, allowing efficient data packing and utilization of available bandwidth without increasing logic complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If existing communication methods are used in SoC circuits, then messages can be transmitted between sub-blocks, but bandwidth is reduced due to unused bits and logic complexity increases when messages span multiple clock cycles
Solution Approach 1:
The patent combines multiple pieces of information into a single signaling mechanism. The end-of-message indicator is merged with the data transmission protocol, allowing the receiver to identify message boundaries without requiring separate control signals or complex state machines. This merging reduces both bandwidth waste and logic complexity by consolidating control information within the existing data path.
Solution Approach 2:
The patent changes the parameter representation by using a dedicated bit position or encoding scheme within the data stream to indicate message end. Instead of using complex timing signals or separate control lines, the message boundary information is encoded as a specific parameter state (such as a particular bit pattern or reserved bit value) that can be detected by the receiving sub-block without increasing overall system complexity.
2Quantity of substance
If messages are transmitted across multiple clock cycles, then complete data can be sent, but bandwidth utilization decreases due to unused bits in each cycle
Solution Approach 1:
The patent ensures continuous useful action by maintaining the data stream activity across clock cycles while transmitting messages of varying lengths. The end-of-message indicator allows the receiver to continuously process incoming data without idle waiting periods, ensuring that each clock cycle contributes to meaningful data reception even when messages span multiple cycles. This eliminates bandwidth waste by preventing idle cycles.
Solution Approach 2:
The patent introduces dynamic message length handling where the transmission duration adapts to the actual message size. The end-of-message indicator enables the receiving sub-block to dynamically determine when a message completes, allowing the system to optimize bandwidth utilization by adjusting the active transmission period rather than using fixed-length transmissions with unused trailing bits.
3Loss of information
If traditional signaling methods are used to indicate message boundaries, then messages can be delimited, but the complexity of the receiving sub-block increases
Solution Approach 1:
The patent implements self-service by embedding the message boundary information directly within the data stream itself. The end-of-message indicator is part of the transmitted data, allowing the receiving sub-block to autonomously detect message boundaries without requiring external control signals or complex state management logic. The data carries its own delimitation information, simplifying the receiver's task.
Solution Approach 2:
The patent uses an intermediary signaling mechanism where a specific bit or encoding pattern acts as a mediator between the data payload and the message boundary detection logic. This intermediary element (the end-of-message indicator) translates the variable-length message structure into a form that the receiving sub-block can easily interpret, reducing complexity by providing a clear, unambiguous signal for message completion.
Data Source
AI summary
An integrated circuit including at least two interconnected sub-blocks in a System-on-Chip (SoC) arrangement and a method for communicating data in the integrated circuit are provided. The method includes transmitting a first signal asserting that a first sub-block is ready to transmit data to a second sub-block, receiving a second signal asserting that the second sub-block is ready to receive data from the first sub-block and transmitting data including one or more contiguous messages via a third signal from the first sub-block to the second sub-block. The first signal includes information that enables the second sub-block to determine a position of the end of the last message in the contiguous messages.