SoC Multi-Display Data Transmission via Single Serial Interface
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Solution Overview
Problem
Multi-display systems require significant computation and hardware resources, making them unsuitable for mobile devices that need low power consumption and small hardware layout areas due to the need for multiple physical channels and transmitters.
Innovation Solution
A System on Chip (SoC) with a data transmission circuit that uses a high-speed serial interface to transmit data packets to multiple displays, adjusting frame rates and controlling transmission timings using a tearing effect signal, allowing for efficient data transmission over a single channel.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If N physical channels and N transmitters are used to transmit data to N displays, then data transmission capability is improved, but power consumption and hardware layout area increase
Solution Approach 1:
The patent merges N separate physical channels and N transmitters into a single shared physical channel and single transmitter. The host controller transmits data packets for multiple displays sequentially over this single channel, using frame rate adjustment signals to coordinate transmission timing and avoid data loss, thereby reducing power consumption and hardware area while maintaining multi-display capability
Solution Approach 2:
The patent implements periodic action by transmitting data packets for different displays in alternating time slots over the shared channel. The host controller uses frame rate adjustment signals to control the transmission timing, allowing each display to receive its data at appropriate intervals without requiring dedicated continuous channels, thus reducing overall system power consumption
2Productivity
If N physical channels and N transmitters are used to transmit data to N displays, then data transmission capability is improved, but hardware layout area increases
Solution Approach 1:
The patent merges N separate physical channels and N transmitters into a single shared physical channel and single transmitter. The host controller transmits data packets for multiple displays sequentially over this single channel, using frame rate adjustment signals to coordinate transmission timing and avoid data loss, thereby reducing power consumption and hardware area while maintaining multi-display capability
Solution Approach 2:
The single physical channel and transmitter are designed to serve multiple displays universally. The host controller dynamically assigns transmission time slots to different displays based on their frame rates and data requirements, allowing the same hardware resources to fulfill multiple display functions simultaneously, thus reducing hardware layout area
3Use of energy by moving object
If a single high-speed serial interface is used to transmit data to multiple displays, then power consumption and hardware area are reduced, but transmission timing control complexity increases
Solution Approach 1:
The patent implements feedback mechanisms where the host controller monitors the transmission status and frame rate requirements of multiple displays, then dynamically adjusts the transmission timing of data packets accordingly. The controller uses frame rate adjustment signals to synchronize data transmission with each display's refresh rate, ensuring timely delivery without requiring complex dedicated hardware for each display
Data Source
AI summary
A system on chip (SoC) for transmitting data packets to a display driver integrated circuit (IC) controlling a plurality of displays is provided. The SoC includes a first register, and a central processing unit (CPU) configured to set first values in the first register to adjust a frame rate of each of the displays. A tearing effect (TE) signal detection circuit is configured to detect a TE signal output from the display driver IC. A data transmission circuit is configured to generate a plurality of frame rate adjustment signals using the detected TE signal and the first values and to control transmission timings of the data packets transmitted to the displays using the frame rate adjustment signals.