SOC Multiple I/O Interfaces Dynamic Topology Selection

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Solution Overview

Problem

In communications systems with multiple devices configured in PCI I/O tree topology, inter-device data transfer latency is high due to sequential data transmission via a single I/O interface, and devices with multiple I/O interfaces cannot fully utilize available bandwidth.

Innovation Solution

A System On Chip (SOC) unit with multiple physical I/O interfaces is enabled to select either a single interface for sequential data transmission or multiple interfaces for random order transmission based on the underlying topology, allowing for efficient data transfer by aggregating multiple I/O interfaces when permissible.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If data is transmitted sequentially via a single I/O interface following PCI topology, then transmission order is maintained, but data transfer latency increases

Engineering Contradiction:
Improvetransmission orderVSAvoiddata transfer latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The system dynamically adapts the transmission topology based on the data stream characteristics. For out-of-order data streams, it switches to a non-PCI topology that allows parallel transmission via multiple I/O interfaces, reducing latency. For in-order data streams, it maintains PCI topology to ensure proper ordering. This dynamic adaptation resolves the contradiction by allowing the system to optimize for speed when ordering isn't required while maintaining reliability when it is.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The invention changes the topology parameter from fixed PCI to variable topology (PCI or non-PCI) based on data stream properties. By detecting whether data requires in-order transmission, the system adjusts the transmission mode accordingly, enabling faster parallel transmission for suitable data while maintaining sequential transmission for data requiring order, thus resolving the latency-ordering contradiction.

Inventive Principle:
Principle #35Parameter changes

2Productivity

If data is transmitted via multiple I/O interfaces in parallel, then bandwidth utilization increases, but transmission order cannot be guaranteed

Engineering Contradiction:
Improvebandwidth utilizationVSAvoidtransmission order
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The system applies different transmission qualities to different data streams based on their requirements. Data streams that can tolerate out-of-order delivery utilize multiple I/O interfaces for high-speed parallel transmission, while data streams requiring strict ordering are routed through the single I/O interface maintaining PCI topology. This local differentiation allows the system to maximize bandwidth for suitable data while preserving ordering where needed.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The transmission mode is dynamically selected based on data stream characteristics. The system detects whether each data stream requires in-order transmission and adjusts the topology accordingly, enabling parallel multi-interface transmission for data that doesn't require ordering while maintaining sequential single-interface transmission for data that does, thus achieving high bandwidth utilization without compromising reliability for ordering-critical data.

Inventive Principle:
Principle #15Dynamics

3Quantity of substance

If a device uses multiple I/O interfaces, then available bandwidth increases, but the device cannot take full advantage of the bandwidth under PCI model

Engineering Contradiction:
Improveavailable bandwidthVSAvoidbandwidth utilization
Core Design Contradiction:
Quantity of substanceVSProductivity

Solution Approach 1:

The device dynamically switches between PCI and non-PCI topologies based on the data stream requirements. When data streams are identified as suitable for parallel transmission (out-of-order tolerant), the device activates multiple I/O interfaces operating in parallel under non-PCI topology, fully utilizing the available bandwidth. For data requiring ordering, it uses PCI topology. This dynamic approach enables the device to actually achieve the high bandwidth utilization that its multiple interfaces are capable of, rather than being constrained by the sequential PCI model for all transmissions.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The invention segments data streams based on their ordering requirements and routes them through different transmission paths. Data streams suitable for parallel transmission are segmented and distributed across multiple I/O interfaces, allowing each interface to operate independently at full capacity. This segmentation enables the device to fully exploit the aggregate bandwidth of multiple interfaces for appropriate data, resolving the contradiction between having multiple interfaces and being able to utilize their full bandwidth potential.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS8718065B2Transmission using multiple physical interface
Publication Date: 2014.05.06 AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LTD
  • US8718065B2 patent drawing
  • US8718065B2 patent drawing
  • US8718065B2 patent drawing

AI summary

A method to transmit data using a device having a plurality of physical input/output (I/O) interfaces is provided. The method comprises receiving data and determining a topology according to which data is to be transmitted. Data is transmitted in sequential order via a single physical interface for a first topology and in random order via a plurality of physical interfaces for a second topology.A System On Chip (SOC) unit enabled to transmit data via one or more physical interfaces is provided. The SOC comprises a processor and a network interface including multiple physical input/output (I/O) interfaces coupled to the processor. In response to receiving data for transmission, the processor is enabled to select a single I/O interface for sequential data transmission according to a first topology or select multiple physical I/O interfaces for random order data transmission according to a second topology.