3D SoC Network Layers for Shorter Data Routing Paths
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Solution Overview
Problem
Conventional System on Chip (SoC) designs face challenges in efficiently routing communication subsystems due to limited space on the substrate, leading to communication delays and increased power usage.
Innovation Solution
The SoC design incorporates multiple network layers positioned above, below, or adjacent to device layers, allowing for more efficient routing of communication subsystems without obstruction by components on the device layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple network layers are added to provide more routing paths, then communication efficiency improves, but device complexity increases
Solution Approach 1:
The patent transitions from two-dimensional routing on a single substrate to three-dimensional routing across multiple stacked layers. Network layers are positioned above, below, or adjacent to device layers, creating vertical communication pathways that bypass component obstructions on the substrate plane. This dimensional expansion provides additional routing dimensions without requiring increases in substrate area.
Solution Approach 2:
The communication subsystem is segmented into multiple independent network layers, each capable of handling specific communication traffic. This segmentation allows different layers to be optimized for different purposes (e.g., high-speed interconnect, memory access, I/O communication) and enables parallel communication paths, improving overall system throughput while distributing complexity across modular layers.
2Adaptability or versatility
If communication paths are routed around components to avoid blockages, then routing flexibility improves, but communication path length increases
Solution Approach 1:
Instead of routing communication paths around components on the same substrate plane, the patent utilizes vertical pathways through stacked network layers. Components on the substrate do not block vertical communication between network layers, enabling direct point-to-point connections that minimize path length while maintaining routing flexibility for different communication scenarios.
Solution Approach 2:
Network layers act as intermediary structures between components on the substrate and memory or I/O devices. These intermediary layers provide dedicated communication channels that bypass component blockages, allowing data to travel through the vertical dimension rather than being forced to route laterally around obstacles on the substrate plane.
3Productivity
If more buses and crossbars are added to handle increased component communication, then communication capability improves, but power usage increases
Solution Approach 1:
The patent replaces the traditional planar expansion of buses and crossbars with vertical stacking of network layers. This dimensional change reduces the physical length of communication paths, thereby reducing dynamic power consumption associated with signal switching and transmission. Shorter paths also reduce capacitive loading and signal integrity issues, further lowering power requirements.
Solution Approach 2:
The patent replaces the mechanical/expansion-based approach of adding more buses and crossbars with a field-based electromagnetic communication approach through standardized network interface connections. This substitution enables more efficient data transmission with lower power consumption by utilizing established communication protocols and optimized signal paths through the network layers.
4Speed
If L2 cache memory size is increased to reduce processor wait time, then processing speed improves, but available space around processor die is limited
Solution Approach 1:
The patent extends the L2 cache memory capacity by utilizing the vertical space in stacked network layers above or below the processor die. This three-dimensional memory expansion provides increased L2 cache capacity without requiring additional lateral substrate area, thereby maintaining processing speed improvements while accommodating space constraints on the substrate plane.
Data Source
AI summary
The technology relates to a system on chip (SoC). The SoC may include a plurality of network layers which may assist electrical communications either horizontally or vertically among components from different device layers. In one embodiment, a system on chip (SoC) includes a plurality of network layers, each network layer including one or more routers, and more than one device layers, each of the plurality of network layers respectively bonded to one of the device layers. In another embodiment, a method for forming a system on chip (SoC) includes forming a plurality of network layers in an interconnect, wherein each network layer is bonded to an active surface of a respective device layer in a plurality of device layer.