3D SoC Network Layers for Shorter On-Chip Data Routing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional System on Chip (SoC) designs face communication delays and increased power usage due to limited space on the substrate, which impedes efficient routing of communication subsystems, leading to processing bottlenecks and reliance on slower cache memory.
Innovation Solution
The implementation of multiple network layers above, below, or adjacent to device layers, such as ASIC and memory layers, using conductive structures like traces, vias, and terminals to route data efficiently, bypassing blockages and reducing communication distances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If components are integrated onto a single substrate in a SoC, then the amount of space taken up by components is reduced, but the number of buses and crossbars increases leading to communication delays and increased power usage
Solution Approach 1:
The patent transitions from two-dimensional routing on a single substrate to three-dimensional routing through multiple stacked layers. Network layers are positioned above and below device layers, creating vertical communication paths that reduce the length of communication paths between components while maintaining high integration density.
2Adaptability or versatility
If the number of components within a SoC increases, then functionality is enhanced, but the number of buses and crossbars increases leading to increased power usage
Solution Approach 1:
By stacking network layers vertically above and below device layers, the patent enables efficient routing to a larger number of components without proportionally increasing the number of long-distance buses. The three-dimensional architecture allows multiple components to share vertical routing resources, reducing overall power consumption while maintaining enhanced functionality.
3Adaptability or versatility
If a larger component is positioned on one layer, then component functionality is improved, but it blocks a portion of the substrate requiring communication subsystem to route around the component
Solution Approach 1:
The patent resolves blocking issues by utilizing the vertical dimension. When a large component blocks the substrate on one layer, the network layers positioned above and below provide alternative vertical pathways for communication. This eliminates the need to route around blocked areas on the same plane, maintaining direct communication paths despite the presence of large components.
4Productivity
If L2 cache memory size is limited due to space constraints around processor die, then processor integration density is maintained, but processor must rely on slower L3 or L4 cache memory
Solution Approach 1:
The patent extends L2 cache memory capacity by utilizing network layers positioned vertically above and below the processor die. This three-dimensional expansion provides additional space for L2 cache without increasing the processor's footprint, enabling larger faster cache while maintaining high integration density and avoiding reliance on slower external cache memory.
Data Source
AI summary
The technology relates to a system on chip (SoC). The SoC may include a plurality of network layers which may assist electrical communications either horizontally or vertically among components from different device layers. In one embodiment, a system on chip (SoC) includes a plurality of network layers, each network layer including one or more routers, and more than one device layers, each of the plurality of network layers respectively bonded to one of the device layers. In another embodiment, a method for forming a system on chip (SoC) includes forming a plurality of network layers in an interconnect, wherein each network layer is bonded to an active surface of a respective device layer in a plurality of device layer.